Data General Corporation

Data General Corporaton

Michael B Druke

David H Bernstein

Michael L Ziegler

Ward Baxter, Ii

Richard A Carberry

Karsten Sorensen

Ronald I Gusowski

Thomas M Jones

James Marriot Guyer

Ronald H Gruner

Brett L Bachman

Kenneth D Holberger

Charles J Holland

David L Houseman

Steven Wallach

Richard W Coyle

Carl J Alsing

Edward J Rasala

Edward M Buckley

Roger W March

Stephen R Redfield

Karsten Sorenson

Thomas West

John R Van Roekel

Stefan Kosior

Louis E Drew

Richard L Feaver

A digital data system having a memory with a unique multi-ported memory I/O means. Separate means are provided for communicating with any of several buses. Address information, operands, instructions and Input/Output data may be separately sent and received over various of the buses.

Unique memory for use in a digital data system

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Dual port cache with interleaved read accesses during alternate

A unique frequency synthesizer unit for use in a data processing system I/O interface unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics.

Frequency synthesizer for providing a pseudo-constant frequency signal

A data processing system the central processing unit (CPU) of which is responsive to and executes microinstructions generated by the decoding of macroinstructions so as to provide one or more data processing operations. The system is arranged so that such microinstructions can be supplied to the CPU from a CPU-resident microcode decoding logic or from one or more external microcode decoding units. Each of the external units can identify a macroinstruction which it is capable of decoding and includes logic for externally providing one or more microinstructions which result from the decoding process. If an external microcode unit and the CPU-resident decode logic are both capable of such decoding operation, the external unit overrides the CPU decoding logic and controls the decoding operation externally. The external microcode unit includes logic for monitoring the number of microinstructions supplied to the CPU which have not yet been executed by the CPU.

External microcode operation in a multi-level microprocessor

A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or 'horizontal', microinstructions and a plurality of second or 'vertical', microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more 'modifier' fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations.

Data processing system utilizing a unique two-level microcoding

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Data processing system

A data processing system in which the bits of each stored word in a memory thereof are refreshed periodically. At substantially the same time the refresh operation with respect to each word occurs, an error detection operation also occurs and, if an error is detected in a word that is being refreshed, the error is then corrected and the corrected word is written back into the memory. Thus, errors are continuously being checked with no more use of machine time then is required for the refresh operation. Error correction, when necessary, then takes place at a fixed frequency, a limit thereby being placed on the error correction process. If errors in a work are detected when the word is requested for access by a requestor, the error is corrected before the word is supplied to the requestor but the corrected word is not written back into memory at that time, the word in memory being again detected and corrected at its next refresh operation.

Refresh and error detection and correction technique for a data

A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or 'horizontal', microinstructions and a plurality of second, or 'vertical', microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more 'modifier' fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations. Unique bus protocol signals are generated to prevent simultaneous access to the system bus by two competing system components and to permit substantially immediate control of the systems bus by a component without requiring a CPU decision thereon. Further, a unique system I/O interface unit permits access to certain I/O components via other I/O buses, such unit utilizing a unique polling technique to identify on an updated basis, all components present on one of such other buses. The system I/O interface unit also includes a unique frequency synthesizer unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency.

Data processing system having unique bus control operation

A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation. The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose. The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an input and an A-input and a B-input.

Data processing system using read-only-memory arrays to provide

A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation. The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose. The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.

Data path configuration for a data processing system

Data processing system having a unique CPU and memory tuning

Growing community of inventors

Chelmsford, MA, United States of America

Michael B Druke