Lsi Logic Corporation

Linear Technology Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Analog Devices,inc.

Symbios, Inc.

Lsi Logic Coporation

Michael B Anderson

Gregory Arthur Tabor

Mark J Jander

Brendan John Whelan

Kenneth C Schmitt

Robert C Dobkin

Andrew J Gardner

Robert Loren Reay

Frank Gasparik

David M Weber

Robert Chiacchia

Tahir M Hasoon

Philip A Atkinson

J Spencer Wright

A low supply headroom bandgap voltage reference generation circuit for generating a bandgap reference voltage from a supply voltage can include a first delta base-to-emitter voltage generation circuit, which can include a first Darlington configuration of a first pair of transistors arranged in a differential pair with a second Darlington configuration of a second pair of transistors. A first input to the first Darlington pair of transistors can be connected to an output voltage node of the bandgap voltage reference generation circuit and a second input to the second Darlington pair of transistors can be connected to the output voltage node of the bandgap voltage reference generation circuit via a first delta base-to-emitter-voltage resistor.

Low supply headroom bandgap voltage reference

Method and system for developing low noise bandgap references. A stacked &#x394;Vgenerator is disclosed for generating &#x394;V. The stacked &#x394;Vgenerator includes an error amplifier configured to generate an output based on an error signal provided by a first stack of the &#x394;Vgenerator. The first stack of the &#x394;Vis coupled to a first sub-circuit and the error amplifier to form a closed loop. The first sub-circuit is coupled to a power supply and ground and configured to provide a source current between the power supply and the ground. The stacked &#x394;Vgenerator also includes a second sub-circuit coupled to the output of the error amplifier, the first and second stacks, and the ground, as well as a second stack of the &#x394;Vgenerator, which is coupled to the first stack and the second sub-circuit. The &#x394;Vis measured at outputs of the first and second stacks and equals the sum of individual &#x394;Vs of the first and second stacks.

Method and system for developing low noise bandgap references

A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information.

Monolithic voltage reference device with internal, multi-temperature drift data and related testing procedures

A first and a second group of individual transistors in a voltage reference may collectively function as a first and a second composite transistor with a first and a second emitter area equal to the combined areas of the emitters of the first and the second groups of individual transistors, respectively. The second emitter area may be larger than the first emitter area. The stability of the reference voltage may depend upon the stability of the ratio between the first emitter area and the second emitter area. The first group of individual transistors may not be at the center of an arrangement of the second group of individual transistors. The constant reference voltage may vary due to thermal hysteresis by less than 200 parts per million over a 40 degree centigrade temperature range.

Low thermal hysteresis bandgap voltage reference

A bandgap voltage reference circuit having temperature curvature correction, comprises a bandgap voltage source configured to generate an output voltage, and a novel curvature correction circuit. The correction circuit is responsive to the bandgap voltage source output voltage and connected to apply a curvature correction signal to the bandgap voltage source to compensate for output voltage temperature dependency of the bandgap voltage source.

Bandgap curvature correction and post-package trim implemented therewith

A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Linearization method and apparatus for voltage controlled oscillator

A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

High speed single phase to dual phase clock divider

A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Method and apparatus for providing precise circuit delays

The present invention provides a digital clock recovery circuit, which includes a frequency synthesizer generating a number of clock phase signals. The digital clock recovery circuit also includes a phase interpolation unit, which interpolates the clock phase signals from the frequency synthesizer to increase the number of clock phase signals. Additionally, the digital clock recovery circuit also includes a phase detector, a digital filter, and a phase selection unit. The phase detector has an output connected to a digital filter, which is connected to the phase selection unit. The phase detector sends signals filtered through the digital filter to select clock phase signals input into the phase selection unit from the phase interpolation unit. The output of the phase selector provides the recovered clock signal and also connected to the input phase detector.

Digital clock recovery circuit with phase interpolation

A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.

Clock recovery circuit

A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.

High speed clock recovery circuit using complimentary dividers

A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Fully digital clock synthesizer

A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.

Method and apparatus for doubling a clock signal using phase

A circuit in a semiconductor device for testing jitter tolerance of a receiver in the semiconductor device. The circuit includes a jitter injection circuit that has an output connected to an input in a phase-locked loop circuit. The jitter injection circuit generates an output signal in response to an application of an input signal. The phase-locked loop circuit has an output that generates a clock signal, wherein the clock signal may be altered by the output signal from the jitter injection circuit. The clock signal from the phase-locked loop circuit controls transmission of data at the transmitter. Alteration of the clock signal caused by the jitter injection circuit alters the manner in which the transmitter transmits data.

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Colorado Springs, CO, United States of America

Michael B Anderson