International Business Machines Corporation

Michael Anton Barenys

Robert Allan Faust

Joel Gerard Goodwin

Joel Gerald Goodwin

Douglas Michael Boecker

Paul Phong Nguyen

Chetan Mehta

Michael Youhour Lim

Stephan Otis Broyles

Curtis Ray Genz

Forrest Clifton Gray

William Eldred Beebe

Garth Wade Tschetter

Brent Ray DenHartog

An IC device is disclosed that includes a main IC section, bus switches, switch logic, and address logic as part of the IC device. The IC device is coupled to an IC bus for communicating with other IC devices and an IC bus controller that is also on the IC bus. The switch logic controls a current position of the switches. The IC device is coupled to the IC bus utilizing the switches. The switches control whether the main IC section, the address logic, the switch logic, or a combination of the main IC section, address logic, and switch logic is currently coupled to IC bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the IC device. The IC device will respond to the address that is stored in its address logic.

[object Object]

A method system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch. Thus, the fault can be isolated to a few devices, switches, or bus connections rather than the large number of potential devices, switches, or bus connections that could have potentially caused the fault.

Method for isolating an I2C bus fault using self bus switching device

An apparatus and method for performing surveillance prior to boot-up of an operating system is provided. The apparatus and method include an error detector that monitors a boot-up sequence of a support system for the occurrence of an error. If an error is detected, a unit check signal is output by the error detector. The unit check signal is received by either the support system or an error message output device and a corresponding error message is generated and output for use by a user of the computing system.

Apparatus and method for performing surveillance prior to boot-up of an operating system

A method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I C) buses are provided. Upon resetting a I C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device's address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.

Dynamically allocating I2C addresses using self bus switching device

A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

I2C bus switching devices interspersed between I2C devices

A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data processing system. The BIST signature generated during the BIST is compared with a predetermined BIST signature stored in a vital products data (VPD) module associated with the chip is read. A difference between the generated BIST signature and the predetermined BIST signature is then reported.

Method and apparatus for storing and using chipset built-in self-test signatures

A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

Method and system for detecting bus device configuration changes

A method, system, and computer program product are disclosed for determining the address type of a serial EEPROM in an electronic system. The method includes reading data from at least one location of the EEPROM for a first time and saving the data for future reference. Thereafter, a sequence of transactions is executed that alters the contents of the EEPROM in a prescribed manner if the EEPROM is of a first type. The sequence of transaction leaves the EEPROM in an unaltered state if the EEPROM is of a second type. Data is then read from at least one location of the EEPROM for a second time. The location of the data read from the EEPROM the second time is the same as the location of the data read the first time if the EEPROM is of the first type. The data read the first time and the data read the second time are then compared. If it is determined that the data read the second time does not differ in the prescribed manner from the data read the first time, the type of the EEPROM is identified as the second type. In one embodiment, the indicate steps are repeated to achieve additional assurance that type of the EEPROM is the first type if it is determined that the data read the second time differs in the prescribed manner from the data read the first time. In one embodiment, reading data from the EEPROM for the first time includes, writing an initial byte to the EEPROM for a first time to set the address pointer to a known state if the EEPROM is of the first type. In one embodiment, the sequence of transactions include writing two bytes to the EEPROM, wherein the value of the first of the two bytes is the value of the initial byte written to the EEPROM. In one embodiment, the method includes, prior to reading data from the EEPROM for the first time writing two bytes to the EEPROM if is determined that the EEPROM is configured with an address type indicator field, where the two bytes comprise the 2-byte address of the indicator field in an EEPROM of the second type. In this embodiment, the two bytes of address type indicator information are read from the EEPROM. The contents of the two bytes are indicative of the address type of the EEPROM.

Address type determination for an I2C EEPROM

Polling of devices on an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I.sup.2 C bus is transmitted to the expansion processor which then echos it to the bus master. Each of the target devices on the sub-bus can be polled to determine if they have failed. Failure of a device only affects operation of its sub-bus.

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Austin, TX, United States of America

Michael Anton Barenys