International Business Machines Corporation

Marvell Asia Pte., Ltd.

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Michael Anthony Ziegerhofer

Michael Richard Ouellette

Krishnendu Mondal

Kiran K Narayan

Kevin William Gorman

John Robert Goss

Aravindan J Busi

Igor Arsovski

Paul J Grzymkowski

Deepak I Hanagandi

Darren Lane Anand

Eric D Hunt-Schroeder

Douglas E Sprague

Valerie Hornbeck Chickanosky

Craig M Monroe

Harold Pilo

Troy Joseph Perry

Nancy H Pratt

Suzanne Granato

David J Wager

Valarie H Chickanosky

Kalpesh R Lodha

A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Embodiments of the present disclosure provide an a circuit including: first logic to compare output data from the shift register with output data from error correcting code circuitry (ECC), to output an error signal in response to a data bit output from the shift register being different from a data bit output from the ECC; second logic for receiving the error signal from the first logic gate, and a correctability signal from the ECC, to output an overwrite signal in response to receiving the error signal and the correctability signal; and a selector receiving the overwrite signal and the data bit of the output data from the ECC, and coupled between a data source and an input line to the shift register. The selector causes the shift register to receive the ECC output in response to receiving the overwrite signal.

Circuit and method for soft-error protection in operation of ECC and register

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

Zero test time memory using background built-in self-test

Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

Memory built-in self-test (MBIST) test time reduction

Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.

Programmable counter to control memory built in self-test

A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.

Apparatus for capturing results of memory testing

Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Staggered start of BIST controllers and BIST engines

Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Decreasing power supply demand during BIST initializations

An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

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Jeffersonville, VT, United States of America

Michael Anthony Ziegerhofer