Itt Manufacturing Enterprises, Inc.

Honeywell G.m.b.h.

Harris Corporation

Eagle Technology, LLC

Exelis Inc.

Michael Anthony Wyatt

Edward Allen Hall

Parker Allen Robinson

Perry Kevin Falk

Methods and systems in accordance with the present invention provide an RF spectrum analyzer on a computer chip, such as an integrated circuit. They may provide RF spectrum analyzer functions on a much smaller scale, which is easier to implement, transport and install in other equipment. They present a single chip solution that is smaller, lighter and more compact than conventional systems. Additionally, they may be put in hand held (or smaller) devices.

Method and system for radio frequency (RF) spectral imager on an integrated circuit

A personal area radar is provided to permit a user to be aware of their surroundings. This may be in 360 degrees or any other suitable coverage area and angle. The personal area radar can show objects to the user through fog, smoke, precipitation, darkness and with full 360 degree field of view capability, significantly improving the user's overall situational awareness. They may also be used to view things that are behind solid objects such as in or behind walls or underground. These systems may be highly integrated phased array radar systems mounted on a helmet. They may use small, high frequency radars able to detect solid objects (and/or semi-solid objects) such as people, improvised explosive devices (IED), or other solid objects. These methods and systems may provide the user with 360 degrees view and awareness of objects regardless of external conditions such as weather, darkness or other obstructions.

Method and system for personal area radar

Methods and systems provide an active chip configured for connection to the battery or other component of a host mobile communication device, such as a cellular phone, to thereby add functionality to the host mobile communication device. The system may be installed and used for covert operations (i.e. military and/or law enforcement), adding features such as location tracking and voice recognition and recording to monitor the movement and use of the host mobile device covertly. The system may be used to communicate with other locally enabled systems on a local network instead of communicating through the cellular network, or operate as a radio transceiver or 'push-to-talk' device such as a 'walkie-talkie.' It may be used as a &#x201c;kid tracker&#x201d; location tracking device, to find a lost host mobile device, lost person carrying the host mobile device, or track locations where a host mobile device has been.

Method and system for active chip in a battery

A low dropout (LDO) voltage regulator includes a scaling amplifier for receiving a bandgap voltage, Vbg, and outputting a scaled Vbg. A reference MOSFET device is included for reducing the scaled Vbg by a first voltage Vgs formed across gate and source nodes of the reference MOSFET device. This forms a reduced level of the scaled Vbg. An RC network filters the reduced level of the scaled Vbg and outputs a filtered voltage. An output buffer is included for receiving and increasing the filtered voltage by a second voltage Vgs in order to recover the scaled Vbg. The scaled Vbg is used as the desired regulated voltage output. The second voltage Vgs, which is produced by the output buffer, is equal to the first voltage Vgs, which is produced by the reference MOSFET device.

Low noise, low dropout voltage regulator

A pixel accumulates charge and an active guard ring surrounds the pixel. A buffer has an input terminal coupled to the pixel and an output terminal coupled to the active guard ring. The buffer places a charge potential on the active guard ring that is substantially equal to a charge potential on the pixel. The charge leakage from the pixel is effectively reduced.

Electron imaging pixel leakage reduction

A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the source terminal of the depletion mode FET are directly connected to each other. Additionally, the emitter terminal of the bipolar transistor and the gate terminal of the depletion mode FET are directly connected to each other. The voltage between the collector and emitter terminals, V, is configured to bias the depletion mode FET. The Vvoltage has a value that is equal and opposite to a voltage Vbetween the gate and source terminals of the depletion mode FET.

Composite device having three output terminals

A high power digital to analog converter (DAC) includes (a) an array of n bipolar transistors arranged in a binary sequence, (b) a depletion mode FET and (c) an array of n switches. The collector terminals of each bipolar transistor in the array are tied together. Furthermore, the depletion mode FET includes a source terminal which is directly connected to the collector terminals of each bipolar transistor. The FET also includes a gate terminal connected to a ground potential, and a drain terminal. Each bipolar transistor is sized to be a factor larger than its preceding transistor in the array of n bipolar transistors, for example, twice as large. The array of n switches is controlled by a digital word of n bits. Each of the n switches selectively activates a respective bipolar transistor in the array of n bipolar transistors. As the n switches are selectively activated, the array of n bipolar transistors provides n binary weighted collector currents in the source terminal of the FET. The n collector currents are equal to a sum of the binary weighted collector currents. The drain terminal of the FET provides the same sum of the binary weighted collector currents.

High power and high frequency gallium nitride based digital to analog converter for direct digital radio frequency power waveform synthesis

Methods of forming scalable systems and scalable systems on an integrated circuit (SoC) are provided. First and second radio frequency (RF) systems are disposed on first and second substrates, respectively. A first processor that is configured to process the first RF system is disposed on a substrate separate from the first substrate and a second processor that is configured to process the second RF system is disposed on a substrate separate from the second substrate. The first processor and the first RF system are stacked one on top of the other to configure a first RFSoC and the second processor and the second RF system are stacked one on top of the other to configure a second RFSoC. The first and second RFSoCs are disposed either in a horizontal plane, laterally spaced from each other, or in vertically stacked planes, one above the other.

Scalable radio receiver architecture providing three-dimensional packaging of multiple receivers

A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter includes a comparator for comparing (a) a value corresponding to a loop filter voltage with (b) an analog value formed by a bit of the digital word.

Synthesizer characterization in real time

A low dropout (LDO) voltage regulator includes an output terminal for providing a regulated voltage output to a load, and a plurality of PFETs connected in parallel. Each PFET drains a level of current and the sum of the levels of current are provided as a current output at the output terminal. The LDO voltage regulator also includes a feedback network coupled to the output terminal for providing a voltage feedback signal, and an error amplifier coupled between the plurality of PFETs and the feedback network for sensing a differential voltage. The error amplifier includes an output voltage which is provided to the plurality of PFETs for adjusting the drain of current from each PFET. A summation of the drains of current from each PFET is provided as the current output to regulate the voltage output at the output terminal. Each PFET drains a current level of Iand the summation of the drains of current is the current output I.

Non-invasive load current sensing in low dropout (LDO) regulators

A wideband combiner includes a core amplifier for receiving first and second pairs of differential input signals and providing a single pair of differential output signals. The pair of differential output signals are a combination of the first and second pair of differential input signals and a signal gain is implemented between the received first and second pairs of differential input signals and the single pair of differential output signals. The core amplifier is configured to provide a gain value between the first and second pairs of differential input signals and the single pair of differential output signals. The signal gain is substantially constant across the frequency bandwidth of the core amplifier. A bandwidth peaking network is coupled to the core amplifier and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series.

Ultra wide band, differential input/output, high frequency active combiner in an integrated circuit

A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.

Radiation hardened logic circuits

A wideband mixer includes a core mixer having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals. A steering module is coupled to the core mixer for receiving differential reference signals and providing bi-phase modulated amplified differential output signals. The core mixer is configured to provide a value of gain between the differential input signals and the differential output signals. A bandwidth peaking network is coupled to the core mixer and includes (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series. The first coil and resistor and the second coil and resistor, respectively, are coupled to the core mixer for receiving the amplified differential output signals. The bandwidth peaking network is configured to increase the frequency bandwidth of the core mixer.

Ultra wide band, differential input/output, high frequency active mixer in an integrated circuit

A transconductor and filter circuit is described. In one embodiment, a front end module within the transconductor and filter circuit converts a differential input voltage signal into a differential output current and supplies the output current at a differential output. A filter module coupled to the differential output of the front end module receives the differential output current, converts the output current into an intermediary differential voltage, and filters the differential voltage to obtain a filtered differential output voltage signal having low output impedance.

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Clearwater, FL, United States of America

Michael Anthony Wyatt