International Business Machines Corporation

Other

Michael Anthony Perez

Alongkorn Kitamorn

Louis Rodriguez

Ashwini Kulkarni

Chad J Larson

Steven Vongvibool

Ricardo Mata, Jr

Gordon David McIntosh

David R Willoughby

Mark Walz Wenning

Calvin Charles Paynton

Kris Marie Kendall

Danny Marvin Neal

Richard Allen Kelley

Adalberto Guillermo Yanes

Chetan Mehta

Rafael Graniello Cabezas

Robert G Kovacs

John Daniel Upton

Kanisha Patel

David Lee Randall

Irving G Baysah

Milton Devon Miller, Ii

Christopher Harry Austen

Kiet Anh Tran

Stephen Dale Linam

Michael E Lyons

Paul Gordon Robertson

Pat Allen Buckland

Bradley Ryan Harrington

Sean McNeal

Padmavathy Tamirisa

A system and method for dynamically reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes, e.g., when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Dynamically reassigning virtual lane resources

A system and method for reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.

Reassigning virtual lane buffer allocation during initialization to maximize IO performance

Mechanisms for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Adjusting direction of data flow between I/O bridges and I/O hubs based on real time traffic levels

Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Balancing PCI-express bandwidth

In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Dynamically balancing bus bandwidth

A system, method, and computer program product are disclosed for executing a reliable warm reboot of one of multiple partitions included in a logically partitioned data processing system. The data processing system includes partition hardware. A request to reboot a particular partition is received within the partition where the particular partition includes multiple processors. Prior to executing the reboot request, the partition hardware is set to a predetermined state. The reboot request is then executed within the particular partition. The predetermined state is preferably achieved by resetting the partition hardware to a predetermined state.

System and method for selectively executing a reboot request after a reset to power on state for a particular partition in a logically partitioned system

A method, system, and computer program product are disclosed for improving isolation of I/O errors in logical partitioned data processing systems. A machine check is generated that indicates that an I/O error has occurred in the system. The PCI host bridge (PHB) that generated the machine check is identified. The system includes multiple PHBs, each with its own set of slots. Some of these slots may be enabled for enhanced error handling while others of them are not. The adapters that are not enabled for enhanced error handling and that are coupled to the PHB that generated the machine check are identified. It is then determined that the I/O error occurred in at least one of these slots that are not enabled for enhanced error handling.

Method, system, and product for improving isolation of input/output errors in logically partitioned data processing systems

A method, apparatus, and computer instructions for reporting errors occurring in a data processing system. Responsive to an error occurring in a host bridge in the data processing system, a determination is made as to whether a device required for generating an error report is located below the host bridge. Responsive to the device required for generating an error report being located below a host bridge, the host bridge is isolated from other portions of the data processing system, wherein only a processor analyzing the error is able to access the host bridge. An error reporting process is performed. The error reporting process is able to access the host bridge and the device.

Apparatus for reporting and isolating errors below a host bridge

A method, apparatus, and computer instructions for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge. A value is read from a selected register to form a read value in response to detecting an error. The selected register is reset. Each bit in the read value associated with the error is cleared to form a cleared value. The cleared value is written into the selected register such that errors occurring since the register was cleared are preserved. The error registers below the bridge are scanned in response to an absence of an error being detected in a bridge within the input/output sub-system. A determination is made as to whether the error has previously occurred in response to a presence of an error being found by scanning the registers below the bridge. The error is reported in response to an absence of a determination that the error has previously occurred.

Method and apparatus for analyzing hardware errors in a logical partitioned data processing system

Method, system, and apparatus for allocating memory to a plurality of expansion slots in a data processing system. During initialization, firmware allocates memory among a plurality of expansion slots on a rigid basis. If an input/output adapter functionally connected to one of the plurality of expansion slots requires more memory, the firmware reallocates the memory among the plurality of expansion slots such that the expansion slot occupied by the input/output adapter is allocated sufficient memory. If during runtime, an input/output adapter is hotplugged into the system and requires more memory than allocated to the slot in which the input/output adapter has been inserted, the firmware reallocates memory, first from unoccupied expansion slots and then, if necessary, from selected ones of occupied expansion slots.

Memory map adjustment to support the need of adapters with large memory requirements

A method, system, and apparatus for programming adapter settings in a data processing system is provided. In one embodiment, the data processing system programs a plurality of settings for each of a plurality of adapters using system based parameters. The data processing system then determines whether any of the adapters settings as programmed based on system based parameters are inconsistent with the specific requirements of the specific adapter. If one or more of the settings in any adapter are inconsistent with the adapter's requirements, those settings are reprogrammed using adapter specific parameters to ensure optimal performance of the data processing system with the adapter.

Method of programming I/O adapter settings for optimal performance

A method for prioritizing bus errors for a computing system is provided. A subsystem test is executed on a first subsystem from a plurality of subsystems on a bus system, wherein the subsystem test on the bus system is specific to the first bus subsystem. An output is received in response to executing the subsystem test. In response to the output indicating an error on the first subsystem, a severity level is assessed based on the error. For all subsystems from the plurality of subsystems on the bus system, a subsystem test is executed on each remaining subsystem, wherein each subsystem test on the bus system is specific to each remaining subsystem. An output is received in response to executing each subsystem test. In response to the output indicating an error on any of the remaining subsystems, a severity level is assessed based on the error.

Method for prioritizing bus errors

A method, system, and apparatus for providing data to an I/O adapter from a PCI-to-PCI bus bridge is provided. In one embodiment, once the PCI-to-PCI bus bridge receives a request for data from the I/O adapter, the PCI-to-PCI bus bridge determines whether the requested data is contained within a cached memory within the PCI-to-PCI bus bridge. If the data is contained within the cached memory, then the requested data is provided to the I/O adapter from the cached memory. If the requested data is not within the cached memory, the data is fetched from system memory, then cached in the PCI-to-PCI bus bridge, and sent to the requesting I/O adapter. To ensure that the data in the cached memory within the PCI-to-PCI bridge is not stale, signals are received, periodically or aperiodically, by the PCI-to-PCI bridge from a PCI host bridge indicating whether the data contained within the buffers is stale. If the data is stale, then in some embodiments, the contents of all the buffers are cleared, while in other embodiments, only the contents of the buffers containing data that has been indicated to be stale is cleared.

Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects

A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter. If the number of input interrupt lines is greater than the number of output lines, then interrupt sharing is necessary. The number of input interrupt lines can be determined automatically by scanning all the card slots or can be determined by values stored in lookup tables. The algorithm to determine a logical mapping of the input interrupt lines to the output lines, in cases where interrupt sharing is required, can be based on a number of factors. A simple approach is to distribute the interrupts as equally as possible. Another algorithm may take into account the expected frequency of interrupts based on the device involved. Yet another approach may use a set of predetermined priorities. Since these algorithms are implemented in firmware or software, they can be changed to meet a particular set of needs. Once the mapping is determined, the input interrupt lines are electronically connecting to the output interrupt lines using &ldquo;glue logic&rdquo; associated with the host adapter. After this mapping is accomplished, an interrupt mapping table is built and sent to the operating system.

Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing

A method, system, and apparatus for customizing procedures to be performed during an initialization process in a data processing system is provided. In one embodiment, a class of procedures to omit during the initialization process is determined. This class of procedures may be for example, the omission of identifying and creating nodes for a certain class of drives, such as, for example, all ssa drives. Once procedures to omit from the initialization process are determined, then all other initialization procedures are performed except, of course, for the procedures belonging to the class of procedures determined to be omitted.

Growing community of inventors

Cedar Park, TX, United States of America

Michael Anthony Perez