Mediatek Corporation

Analog Devices,inc.

Mediatek Singapore Pte. Ltd.

Maxim Integrated Products, Inc.

Michael Anthony Ashburn, Jr

Ayman Shabra

Frank Op 't Eynde

Stephen William Harston

Chi-Lun Lo

Nathan T Egan

Khurram Muhammad

Eric G Nestler

Sheng-Jui Huang

Tien-Yu Lo

Jeffrey Carl Gealow

Divya Kesharwani

Abhishek Bandyopadhyay

Charles M Allen

Che-Fu Liang

Paul F Ferguson

Stacy Ho

John M Wettroth

Alberto Riera Sanchez

Patrick Cooney

Adalberto Cantoni

David Paul Smith

Tao He

Tsung-Kai Kao

Joshua M Bamford

Etienne Gerard Moulin

Shuang Jin

Meghan C Kaiserman

Paul Daigle

Meghan Constance Baker

Alberto Sanchez

Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.

Resistive DAC with summing junction switches, current output reference, and output routing methods

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

Methods and circuits for suppressing quantization noise in digital-to-analog converters

A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.

Comparator having a high-speed amplifier and a low-noise amplifier

According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

&#x394;&#x3a3; modulator with excess loop delay compensation

Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

Circuits and methods for inter-symbol interference compensation

A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

VCO-based continuous-time sigma delta modulator equipped with truncation circuit and phase-domain excess loop delay compensation

Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

System and method for measuring the DC-transfer characteristic of an analog-to-digital converter

A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.

Digitally-corrected analog-to-digital converters

Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.

Sigma-delta ADC with dither

A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Segmented fractional-N PLL

An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Continuous-time oversampled converter having enhanced immunity to noise

A continuous-time sigma-delta analog-to-digital converter includes a plurality of integrator stages, in which one of the integrator stages includes a current buffer that drives an integrating capacitor. The analog-to-digital converter includes an outer feedback digital-to-analog converter and an inner digital-to-analog converter. The inner digital-to-analog converter is a current-mode digital-to-analog converter that converts the digital output signal to an analog current feedback signal, which is provided to an output of the integrator stage that includes the current buffer. Both the analog current feedback signal and an input signal provided to the current buffer are integrated by the integrating capacitor.

Direct feedback for continuous-time oversampled converters

A continuous-time sigma-delta analog-to-digital converter includes a first integrator stage to integrate a difference between a first differential signal derived from a differential analog input signal and a second differential signal derived from a quantized output signal, a quantizer and a low pass filter. The first integrator stage has a differential operational amplifier, first, second, third, and fourth input resistors, and a first pair of integrating capacitors. The differential analog input signal is received at first and second input nodes of the converter. The first and third input resistors are coupled in series between the first input node and a first input of the operational amplifier. The second and fourth input resistors are coupled in series between the second input node and a second input of the operational amplifier. The first and second input resistors are coupled to the third and fourth input resistors, respectively.

Continuous-time oversampled converter having passive filter

A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits which limit the voltage across the transistor junctions in the switching circuit to less than the predetermined breakdown voltage.

Low voltage driver for high voltage LCD

An auto-nulled bandgap reference system employing a substrate bandgap reference circuit with primary and auxiliary amplifiers and a switching circuit which in a first mode develops a voltage to null the offset and noise errors of the auxiliary amplifier and then in the second mode uses the nulled auxiliary amplifier to develop a voltage to null the offset and noise errors of the primary amplifier; and a strobe circuit including an output storage device and a strobe control circuit for periodically powering up a bandgap reference circuit to charge the output storage device and powering down the bandgap reference circuit to conserve power.

Growing community of inventors

Groton, MA, United States of America

Michael Anthony Ashburn, Jr