Infineon Technologies Ag

Qimonda Ag

Altis Semiconductor, Snc

Michael Angerbauer

Corvin Liaw

Heinz Hoenigschmid

Milena Dimitrova

Peter Schroegmeier

Bernhard Ruf

A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.

Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell

An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Integrated circuit with Resistivity changing memory cells and methods of operating the same

The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.

Memory circuit including a resistive memory element and method for operating such a memory circuit

A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Resistive memory device and method for writing to a resistive memory cell in a resistive memory device

A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2combinations of the set of combined states into n two-level data bits.

Memory device and method for transforming between non-power-of-2 levels of multilevel memory cells and 2-level data bits

A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

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Freutsmoos, Germany

Michael Angerbauer