Datapoint Corporation

Nxp B.v.

Other

Intellectual Ventures I LLC

Freescale Semiconductor,inc.

Intersil Americas Inc.

Conexant, Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Digitalocean LLC

Lucent Technologies Inc.

Nxp USA, Inc.

Moses Computers, Inc.

Michael Andrew Fischer

Timothy Gordon Godfrey

Wilhelmus J M Diepstraten

William M Cox

Wesley D Hardell

Maarten Menzo Wentink

Vincent Pierre Martinez

Alessio Filippi

Kevin Bruce Traylor

Jayakrishnan Cheriyath Mundarath

Robert A McGowan

Brian Christopher Kahne

Peter H Halpern

James H Nuckols

Roderick Lee Dorris

Floyd H McDougall

John L Moschner

John David Round

Charles Lawrence

Larry W Koos

A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

System on chip with pre-exemption interrupts for partition execution control

A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

Efficient inter-thread communication between hardware processing threads of a hardware multithreaded processor by selective aliasing of register blocks

A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Data processing system having distrubuted registers

A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware devices.

Freedom from interference for aggregated communication channel handling using event-based processor extensions

Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed. In an embodiment, the method includes providing a multithreaded processor with a register file that provides registers for T hardware threads, the register file being organized as a set of B blocks, where each of the B blocks contains N registers and where B is greater than or equal to T, configuring assignments of the B blocks to the T hardware threads such that at least one of the B blocks of the register file and not more than R/N of the B blocks of the register file is assigned to each of the T hardware threads, where R is the number of registers defined by the instruction set architecture of the multithreaded processor and where R/N is an integer, thereby the multithreaded processor supports the T hardware threads with the register file that has less than T&#xd7;R registers, and executing machine instructions on the multithreaded processor, where register numbers in the machine instructions are translated into register file addresses using the configured assignments.

Selectable register file blocks for hardware threads of a multithreaded processor

A processor including a pointer storage that stores pointer descriptors each including addressing information, an arithmetic logic unit (ALU) configured to execute an instruction which includes operand indexes each identifying a corresponding pointer descriptor, multiple address generation units (AGUs), each configured to translate addressing information from a corresponding pointer descriptors into memory addresses for accessing corresponding operands stored in a memory, and a smart cache. The smart cache includes a cache storage, and uses the memory addresses from the AGUs to retrieve and store operands from the memory into the cache storage, and to provide the stored operands to the ALU when executing the instruction. The smart cache replaces a register file used by a conventional processor for retrieving and storing operand information. The pointer operands include post-update capability that reduces instruction fetches. Wasted memory cycles associated with cache speculation are avoided.

Processor with smart cache in place of register file for providing operands

Aspects of the present disclosure are directed to methods and/or apparatuses involving stations () participating in wireless station-to-station communications in which each of a plurality of stations shares a wireless communications channel (). Information is collected wirelessly () from transmissions associated with a first communication protocol and from transmissions associated with a second communication protocol. A current communication environment is dynamically discerned therefrom (), and used to characterize a dynamic relationship of the collected information, which is indicative of respective usage of the wireless communication channel by data transmitted via the respective protocols. Usage of the channel is allocated () for respective communications that use the first and second communication protocols based on the dynamic relationship. Sets of data () are wirelessly transmitted via the first and second communication protocols over the channel, based on the allocated usage.

Wireless vehicular communications with channel allocation involving different protocols

Aspects of the disclosure are directed to methods and apparatuses for wireless vehicular communications involving the transmission of messages using two or more protocols. As may be implemented in accordance with one or more embodiments characterized herein, wireless station-to-station communications are carried out in which a plurality of stations share a wireless communications channel. Information is wirelessly collected respectively from transmissions associated with a legacy communication protocol and another type of communication protocol. A current communication environment of the station is dynamically discerned and characterizes a dynamic relationship of the collected information using the legacy communication protocol relative to the collected information using the other communication protocol. Communications are wirelessly transmitted over the wireless communications channel using the legacy and other communication protocols, by allocating usage of the channel through transmissions of data, via the legacy communication protocol and via the other communication protocol, based on the dynamic relationship.

Wireless vehicular communications with dynamic-based relationships

A novel implementation of a partitioned Medium Access Control (MAC) is disclosed. The illustrative embodiment employs a shared bus that typically is already present in a wireless terminal for communication between an Upper MAC and a Lower MAC. The partitioned MAC implementation therefore does not require any additional communication means between the Upper MAC and Lower MAC, resulting in a lower-cost system. In addition, the Upper MAC and Lower MAC pass native data structures by reference over the shared bus, thereby eliminating the need for drivers to coordinate communication via interrupts, handshaking, etc. The partitioned MAC implementation results in a cost-effective distributed architecture in which the Upper MAC resides in the terminal's host processor and the Lower MAC resides in the terminal's wireless station.

Partitioned medium access control implementation

A technique is disclosed for improving how stations that operate in accordance with different protocols coexist with an access point that operates in accordance with a single protocol. In the illustrative embodiment of the present invention, a station provides timing information to an IEEE 802.11 access point. The access point uses the timing information to determine when it may transmit any available frames to the station, so as not to interfere with any ongoing Bluetooth packet transmissions that are made by the station.

Intelligent downstream traffic delivery to multi-protocol stations

A technique is disclosed that improves the efficiency of transmitting data over multiple shared-communications channels without some of the costs and disadvantages associated with techniques in the prior art. In particular, and in accordance with the illustrative embodiment of the present invention, a data frame is simultaneously transmitted across a plurality of channels, but the acknowledgment frame to the data frame is not. Instead, a plurality of redundant acknowledgment frames are generated and each one is transmitted independently and within each of the channels used to transmit the data frame.

Acknowledging data transmissions in the presence of multiple shared-communications channels

A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller and a plurality of hardware contexts. Each hardware context is capable of storing the current state of one thread in a form that enables the processor to quickly switch to or from the execution of that thread. To enable the processor to be capable of responding to low-latency-tolerant events quickly, each thread&#x2014;and, therefore, each hardware context is prioritized&#x2014;depending on the latency tolerance of the thread responding to the event.

Multi-threaded processor architecture

A technique for enabling a secure, point-to-point wireless connection between a secondary computer (e.g., a personal digital assistant, etc.) and a primary computer (e.g., a notebook, a desktop, etc.) is disclosed. The primary computer is associated with an extended infrastructure through an access point. The present invention enables the secondary computer to communicate either with the associated primary computer or with an extended network indirectly through the access point.

Technique for achieving connectivity between telecommunication stations

A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.

System and method for reducing power consumption of memory in an I/O controller

A technique is disclosed for conveying extended functionality control and management information in networks. Enhanced stations encode the control and management information in pre-existing messages. In accordance with the illustrative embodiment of the present invention, the enhanced stations perform the encoding without the need to create nonstandard or proprietary frame formats. Unenhanced stations that are present in the same network as enhanced stations react to the encoded information in a benign way.

Growing community of inventors

San Antonio, TX, United States of America

Michael Andrew Fischer