US Government As Represented by the Secretary of the Army

Michael Andrew Derenge

Tsvetanka Zheleva

Pankaj B Shah

Kenneth A Jones

Daniel Jonathan Ewing

Shah Pankaj

Carl Emmett Hager, Iv

An improved methodology for annealing group III-nitride semiconductor device structures using novel weighted cover systems that protect an annealing cap during the semiconductor annealing process is disclosed. The weighted cover system is configured for preventing the escape of nitrogen from the capped semiconductor during annealing. In one particular embodiment, the weighted cover system comprises a protective cover configured to be placed on the capped semiconductor during the anneal, and one or more weights configured to be placed on the protective cover to provide sufficient downward force to the protective cover that is placed on the capped semiconductor.

Methodology for annealing group III-nitride semiconductor device structures using novel weighted cover systems

A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.

Low-defect density gallium nitride semiconductor structures and devices thereof

Low-defect density gallium nitride semiconductor structures and fabrication methods

A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250&#xb0; C.; and removing the first and second layers from the Group III-nitride semiconductor.

Method using multiple layer annealing cap for fabricating group III-nitride semiconductor device structures and devices formed thereby

Growing community of inventors

Columbia, MD, United States of America

Michael Andrew Derenge