Dew Engineering and Development Limited

Synopsys, Inc.

Other

Cypress Semiconductor Corporation

Elliptic Technologies Inc.

Michael Andrew Borza

Neil Hamilton

Neil Teitelbaum

Stephen J Borza

Andrew Alexander Elias

A A Jithra Adikari

Stephen Davis

Qidao Li

François Bourdon

Kurt S Schwartz

Laurence Hamid

Michael Bowler

Stephen J Davis

Michael James Lewis

Adam Cron

Patrick J Gallagher

Scott Andrew Hamilton

John Douglas Wong

Fabio G DeWitt

Gordon Sean Freedman

Bandi Chandra Sekhar Reddy

Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

Hardware-based obfuscation of digital data

A method is disclosed for providing first data and a first secret key to a cipher processor for ciphering. The first data is ciphered in accordance with a first cipher process and the first secret key to provide output data. Before ciphering of the first data, extra data is inserted within the cipher processor for ciphering in accordance with at least a portion of said first cipher process. The extra data is inserted within a sequence of cipher processor operations for obfuscating the output data.

System and method for cryptographic processing in a time window

A method for ciphering protected content communicated between a first device and a plurality of devices over a plurality of channels comprises performing authentication between the first device and each of the plurality of devices to create two or more shared key and initialization vector pairs allowing the ciphering of the protected content; generating a key stream for each of the channels based on a selected one of the two or more of shared key and initialization vector pairs; maintaining a buffer for each channel, each of the buffer containing the key stream generated for the corresponding channel; and ciphering data incoming on a selected channel using the selected key stream from the buffer corresponding to the selected channel.

Multiport content encryption engine

The invention relates to the field of data packet management, and more specifically to the field of managing of data packets in such a manner that power consumption is reduced, such reduction being especially beneficial for portable device applications. In accordance with an embodiment of the invention there is provided a method of handling and manipulating data wherein padding and unpadding operations for a packet of data are performed at the transmission/reception of a packet from a network, and data handling is minimized within the portable device. According to another embodiment of the invention there is provided a method of encryption for packet data absent the padding data.

Method for inserting and removing padding from packets

A system and method to automatically provision a trusted virtual appliance (VA) (which may include one or more virtual machines (VM)) for installation onto a consumer-owned acceptable device (COAD) where the system and method may create a provision the VA for the COAD without human interaction and a COAD may install a received trusted VA without human interaction, and the VM of a VA may operate independently of other applications on the COAD other than a VM supervisory program such as a hypervisor.

Architecture, system and method for creating and employing trusted virtual appliances

A processor is disclosed for ciphering of first data. The processor includes a key store and a first data store. In use the processor for ciphering the first data in accordance with a first cipher process and a first secret key to provide output data, during ciphering of the first data inserting within the cipher processor other data for ciphering in accordance with at least a portion of the first cipher process, the other data inserted within a sequence of cipher processor operations and scheduled for obfuscating the output data.

System and method for multichannel cryptographic processing

A method of improving the efficiency of an encryption/decryption process implementing the NIST FIPS 197 standard which includes a substitution box (S-box) and an inverse substitution (inverse S-box), comprises concatenating the S-box and inverse S-box to form a combined lookup table, and folding the concatenated table to generate a folded lookup table. The folded lookup table may be indexed for an encryption operation and for a decryption operation using a signal indicative of whether encryption or decryption is used.

Area efficient cryptographic method and apparatus

A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.

System and method for dynamic tuning feedback control for random number generator

A method is disclosed for intermixing a first stream of data and a second stream of data. An associated first secret key is expanded to form a first associated expanded secret key. An associated second secret key is expanded to form a second associated expanded secret key. The first stream of data and the second stream of data are intermixed to form a combined stream of data, which is ciphered. The combined stream of data is de-multiplexed after ciphering thereof and provided at an output port.

Cryptographic sequencing system and method

A memory device including a ferroelectric memory array is described. In one embodiment, the ferroelectric memory array includes a user memory space. The memory device includes control logic configured to provide external read and write access for a host system to the user memory space upon authentication between the host system and the memory device. The host system accesses the user memory space and communicates with the control logic through address, data and control buses. The memory device further includes memory interface configured to interface between the address, data and control buses and the control logic, and through which the host system communicates with the control logic, and a cipher engine in communication with the control logic and the memory interface, the cipher engine comprising a random number generator and an encryption/decryption block. Other embodiments are also described.

Authenticating ferroelectric random access memory (F-RAM) device and method

Method for inserting/removal padding from packets

An F-RAM authenticating memory device and method providing secure mutual authentication between a Host system and a memory in order to gain read/write access to the F-RAM user memory contents. The device and technique of the present invention uses an Advanced Encryption Standard AES128 encryption module in conjunction with a true hardware random number generator and basic exclusive OR (XOR) functions in order to achieve a secure algorithm with a relatively small amount of processing. Due to inherently faster write times than that of conventional floating gate non-volatile memory technologies, the use of F-RAM significantly reduces the time available to interfere with a critical security parameter (CSP) update. Moreover, unlike floating gate technologies, F-RAM's read vs. write current signature is balanced making it less prone to side channel attacks while also providing relatively faster erase times.

An architecture for use in packet processing and supporting compatibility with current BSD implementations for packet processing is proposed wherein two MBUF formats are supported. A first format includes a header portion and a data portion for storing data therein. A second format includes a header portion but is absent a data portion and is for addressing data stored within a cluster and external to the MBUF itself.

Packet memory processing system having memory buffers with different architectures and method therefor

A method for reducing the memory requirements of executing ciphering processes is disclosed which utilizes sequential key extraction and ciphering. By providing a base key for extracting therefrom multiple first sequential security keys; each key is sequentially extracted and employed. During the process overwriting of each sequential security key occurs with the next subsequently extracted sequential security key. In this manner memory requirements are lowered, power consumption reduced which are important in mobile applications.

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Ottawa, Canada

Michael Andrew Borza