Enhanced Memory Systems, Inc.

Michael Alwais

Kenneth J Mobley

Michael Peters

An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.

Enhanced signal processing random access memory device utilizing a DRAM

An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.

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Colorado Springs, CO, United States of America

Michael Alwais