Ramtron International Corporation

Michael Alwais

Kurt Schwartz

Donald G Carrigan

L David Sikes

A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.

Ferroelectric random access memory configurable output driver circuit

An octal transparent latch or D-type register (or flip-flop) integrated circuit device may be packaged in an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally ferroelectric capacitors, using well known ferroelectric materials such as PZT, SBT, or BST or other ferroelectric materials. EEPROM, Flash, SNOS, or other writeable nonvolatile technologies can also be used. In a particular embodiment disclosed herein, the nonvolatile elements of the integrated circuit device are written only when the latched state changes to reduce write endurance changes thereto and data changes on either the input or output data lines that are not latched have no effect.

Nonvolatile octal latch and D-type register

An integrated circuit memory device and method incorporating Flash and ferroelectric random access memory arrays integrated on a common substrate. The present invention allows a relatively small amount of ferroelectric random access memory to mitigate many of the erase and write time disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (&ldquo;ASIC&rdquo;), a block of ferroelectric memory that is sized to match the largest sector of Flash memory can effectively compensate for the latter's slow erasure and write times.

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Newbury Park, CA, United States of America

Michael Alwais