Motorola Corporation

Motorola Solutions, Inc.

Motorola Mobility LLC

Michael Allen Schuette

Philip E May

Kent Donald Moat

Raymond Brooke Essick, Iv

Ali Saidi

Silviu Chiricescu

James M Norris

Brian Geoffrey Lucas

Michael D Pearce

S David Silk

David A Hume

Raymond B Essick

Brian Jeffrey Lucas

A method and apparatus for providing a service at an incident scene is provided herein. During operation, a device will enter a geographic area (e.g., an incident scene), join a local-area network (LAN), and determine what services are presently being offered by other devices on the LAN. From a list of services deployed on the device, a determination is then made as to what services the device will run, and those services are then offered to all devices on the LAN.

Method and apparatus for providing services to a geographic area

A method, information processing system, and network that expands safety network coverage for first responder safety within a building environment. Activity of at least one independent network () is monitored. The independent network () includes at least a safety network. An emergency signal is received from the at least one independent network (). Communication between at least the safety network () and a First responder network () is automatically bridged in response to receiving the emergency signal so as to manage data control and bandwidth allocation between the safety network and the first responder network. Other networks that may also be bridged with the first responder network so as to manage data control and bandwidth allocation among the various networks include IT networks and building automation networks in order to expand first responder network coverage.

Communications network and management arbitrator

A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to 'valid' once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to 'invalid' in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to &#x2018;valid&#x2019;. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.

Method and apparatus for nested instruction looping using implicit predicates

A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.

Memory address generation with non-harmonic indexing

A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

Streaming vector processor with reconfigurable interconnection switch

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Scheduler of program instructions for streaming vector processor having interconnected functional units

A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Method of programming linear graphs for streaming vector computation

A memory interface device ( ) providing a fractional address interface between a data processor ( ) and a memory system ( ) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator ( ) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit ( ) coupled to the address generator ( ) for retrieving first and second data values from the memory system ( ) at the first and second memory addresses, respectively. The device also includes a data access unit ( ) for interpolating between the first and second data values and passing the interpolated value to the data processor ( ). The memory interface has application in a variety of data processing systems, including digital signal processors and streaming vector processors.

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Wilmette, IL, United States of America

Michael Allen Schuette