Nxp Usa, Inc.

Freescale Semiconductor,inc.

Motorola Corporation

Actel Corporation, Inc.

University of Florida Research Foundation, Incorporated

Michael Alan Sadd

Anirban Roy

Jon Scott Choy

Craig T Swift

Bruce E White

Ramachandran Muralidhar

Gowrishankar L Chindalore

Sucharita Madhukar

John L McCollum

Cheong Min Hong

Leo Mathew

Fethi Dhaoui

Bruce L Morton

Rajesh A Rao

Robert F Steimle

Erwin J Prinz

Michael Garrett Neaves

Bich-Yen Nguyen

Sufi Zafar

Chitra K Subramanian

David L O'Meara

Frank Kelsey Baker, Jr

Ko-Min Chang

Chen He

Thuy B Dao

Zhigang Wang

Hector Adrian Sanchez

Srikanth Balaji Samavedam

Frank W Hawley

Vishal P Trivedi

Tushar Praful Merchant

Mohamed S Moosa

Timothy J Strauss

Sriram Kalpat

Bo Jiang

Jerry G Fossum

Daniel T Pham

Richard Chan

George Wang

Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Testing disruptive memories

A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

Memory with sense amplifiers

A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Sense path circuitry suitable for magnetic tunnel junction memories

An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.

Systems and methods for non-volatile flip flops

A memory includes a global reference circuit for generating a signal that controls the resistance of a plurality of reference devices used to read data in memory cells by sense amplifiers of the memory. The signal is generated by an output of an operational amplifier of the global reference circuit. The operational amplifier includes a first input whose voltage is set by flowing current through a reference circuit and a second input whose voltage is set by flowing current through a master reference device. The signal controls the resistance of the master reference device such that the voltages of the inputs of the operational amplifier match.

Memory with a global reference circuit

The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Programmable resistive elements as variable tuning elements

A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. The first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit.

A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.

Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory

The present disclosure provides embodiments for methods and memory devices. One embodiment of a memory device includes a first volatile memory cell having a first volatile access transistor with a current electrode coupled with a first volatile bit line; a first non-volatile memory cell having a first non-volatile access transistor with a current electrode coupled with a first non-volatile bit line; and a transfer circuit coupled between the first volatile bit line and the first non-volatile bit line. The transfer circuit is configured to: couple data latched from the first volatile bit line with the first non-volatile bit line during a store operation, and couple the first volatile bit line with the first non-volatile bit line during a restore operation.

Memory device with combined non-volatile memory (NVM) and volatile memory

A memory device includes a first line coupled to a first terminal of a first memory cell, a second bit line coupled to a first terminal of a second memory cell, a sense amplifier coupled to a second end of the first bit line and a second end of the second bit line, a capacitor including a first terminal coupled to a first input of the sense amplifier and a second terminal coupled to a switch. The switch couples the second terminal of the capacitor to the second bit line during a calibration phase of a read operation and to the first bit line during a sense phase of the read operation. A current/voltage source drives current on the first bit line while the second line is floating during the calibration phase, and drives current on the second bit line while the first bit line is floating during the sense phase.

Magnetic random access memory (MRAM) and method of operation

In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read.

Sense amplifier circuit

A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a transistor that includes a current terminal. The memory read operation includes two phases. During a first phase, a terminal of the capacitor is coupled to a first cell. During a second phase, the terminal of the capacitor is coupled a second cell.

A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.

A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. The first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node. The second terminal of the first resistive element is coupled to a first source line voltage. The second terminal of the second resistive element is coupled to a second source line voltage. A first transistor includes a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node.

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Austin, TX, United States of America

Michael Alan Sadd