Motorola Corporation

Michael Alan Mateja

John C Potter

Alfred Larry Crouch

Donald L Tietjen

Grady L Giles

Matthew D Pressly

Daniel T Marquette

Clark Gilson Shepard

Tulley M Peters

Jason E Doege

Lee Allen Corley

Odis Dale Amason, Jr

A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device ( ), converting the first test vector from an input pin format into state data associated with the logic device ( ), and searching the internal state data to identify a set of last shift transitions ( ). A method of making a logic device having a specification frequency, the method including the steps of providing an integrated circuit, testing the integrated circuit using a scan test pattern at a frequency at least as great as the specification frequency ( ), performing a diagnosis procedure to produce a diagnosis result ( ), and producing the integrated circuit in a final form after the diagnosis result indicates a non-functional problem ( ). The diagnosis result indicates at least one of a non-functional problem and a speed problem.

Method of making logic devices

A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device (10), converting the first test vector from an input pin format into state data associated with the logic device, and searching the internal state data to identify a set of last shift transitions. A method of making a logic device having a specification frequency, the method including the steps of providing an integrated circuit, testing the integrated circuit using a scan test pattern at a frequency at least as great as the specification frequency, performing a diagnosis procedure to produce a diagnosis result, and producing the integrated circuit in a final form after the diagnosis result indicates a non-functional problem. The diagnosis result indicates at least one of a non-functional problem and a speed problem.

Method of testing logic devices

Circuitry is implemented within an integrated circuit ('chip') (101) which is an IEEE 1149.1 compliant device capable of performing JTAG testing (104), such as an EXTEST or CLAMP testing procedure. Upon exiting of either of these procedures, the input/output pins (210) of the chip are placed in a known state, which may be a high impedance state.

Data processing system for performing a test function and method therefor

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.

Scan based testing of an integrated circuit for compliance with timing

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Austin, TX, United States of America

Michael Alan Mateja