International Business Machines Corporation

Jeol Usa, Inc.

Michael Abramovich Gribelyuk

Alessandro Cesare Callegari

Sufi Zafar

Vijay Narayanan

Dianne L Lacey

Paul Charles Jamison

Fenton Read McFeely

Oleg Gluschenkov

Renee Tong Mo

Eduard Albert Cartier

Vamsi Krishna Paruchuri

Deborah A Neumayer

Dae-Gyu Park

Kwong Hon Wong

Bruce Bennett Doris

Cyril Cabral, Jr

Andres Bryant

Katherine Lynn Saenger

Michael Patrick Chudzik

Shreesh Narasimha

Evgeni Petrovich Gousev

Rajarao Jammy

Edward P Maciejewski

Christopher Peter D'Emic

Alessandro Curioni

Atul Champaklal Ajmera

Pushkar Ranade

Woo-Hyeong Lee

Wanda Andreoni

Carlo A Pignedoli

Percy V Gilbert

Kevin K Chan

Keith Kwong Hon Wong

Judson Robert Holt

Tze-Chiang Chen

Yun-Yu Wang

Barry P Linder

Henry K Utomo

John Christopher Arnold

Huajie Chen

Werner A Rausch

Joseph Francis Shepard, Jr

Naim Moumen

Anthony Gene Domenicucci

Ashima B Chakravarti

John Gerard Gaudiello

Harald F Okorn-Schmidt

Anita Madan

Douglas Andrew Buchanan

Dan Mihai Mocuta

Michelle Leigh Steen

John Bruley

Paul Andrew Ronsheim

Rashmi Jha

Glenn A Biery

Young-hee Kim

Joseph S Newbury

Theodore Harold Zabel

Ryan Matthew Mitchell

Masahiro Kawasaki

Fenton R Feeney

Romany Ghali

Evengi Gousev

Joseph P Shepard, Jr

Fenton R Mcfeely

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

High performance CMOS circuits, and methods for fabricating same

A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000&#xb0; C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 &#x212b; in a p-metal oxide semiconductor (pMOS) device.

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The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

A compound metal comprising MONwhich is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MONcompound metal. Furthermore, the MONmetal compound of the present invention is a very efficient oxygen diffusion barrier at 1000&#xb0; C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 &#x212b; in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

Metal oxynitride as a pFET material

A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.

Method for tuning the threshold voltage of a metal gate and high-k device

The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 &#x212b;; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 &#x212b;.

High-temperature stable gate structure with metallic electrode

A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400&#xb0; C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures

A compound metal comprising MONwhich is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MONcompound metal. Furthermore, the MONmetal compound of the present invention is a very efficient oxygen diffusion barrier at 1000&#xb0; C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 &#x212b; in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50&#xb0; C. above the 550&#xb0; C. crystallization temperature of silicon.

Polycrystalline silicon layer with nano-grain structure and method of manufacture

The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cm/V-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-k gate stacks with high mobility

A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the 'plug') remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

Chemical treatment to retard diffusion in a semiconductor overlayer

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Stamford, CT, United States of America

Michael Abramovich Gribelyuk