Matrix Semiconductor, Inc.

Sandisk 3d LLC

Sandisk Corporation

Twin Creeks Technologies, Inc.

Michael A Vyvoda

James Montague Cleeves

N Johan Knall

Calvin K Li

Vivek Subramanian

Manish Bhatia

Scott Brad Herner

S Brad Herner

Christopher S Moore

Christopher John Petti

Andrew J Walker

Igor G Kouznetsov

Steven J Radigan

Samuel Vance Dunton

Derek Bosch

Matthew P Crowley

Aditya Agarwal

David Russell Friedman

Joseph James Tringali

Srinivasan Sivaram

K Leo Zhang

Christopher R Moore

Methods for bonding a donor wafer to a receiver element and transferring a lamina from the donor wafer to the receiver element are disclosed herein. The donor wafer may be, for example, a monocrystalline silicon wafer with a thickness of from about 300 microns to about 1000 microns, and the lamina may be may be less than 100 microns thick. The receiver element may be composed of, for example, metal or glass, and the receiver element may have dissimilar thermal expansion properties from the lamina. Although the lamina and the receiver element may have dissimilar thermal expansion properties, the methods disclosed herein maintain the integrity of the bond between the lamina and the receiver element.

Methods of transferring a lamina to a receiver element

A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.

Process for fabricating a dielectric film using plasma oxidation

A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are 'rightside-up' with antifuse over the metal, and those on even levels are 'upside down' with metal over the antifuse. Both antifuses are preferably grown oxides.

Rail Schottky device and method of making

A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Electrically isolated pillars in active devices

A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.

Low resistivity, C54-phase TiSiis formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750&#xb0; C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi, forming a low-resistivity, C54-phase TiSifilm on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSiis reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (&#x3c;0.3 &#x3bc;m) of low-resistivity, C54-phase TiSifilms on heavily doped polysilicon are thus achieved.

Low resistivity titanium silicide on heavily doped semiconductor

A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

Patterning three dimensional structures

Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Metal structures for integrated circuits and methods for making the same

The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

Integrated circuit feature layout for improved chemical mechanical polishing

A method for forming a contact in a three dimensional monolithic memory is disclosed. In a preferred embodiment, the method comprises depositing a conductive layer over and in contact with a plurality of antifuses, wherein said antifuses are part of a story of active devices formed above a substrate; patterning and etching said conductive layer and insulating dielectric to form a contact void; and filling the contact void, wherein the conductive layer does not comprise silicon.

Method for making contacts in a high-density memory

A multiple-mode memory includes a three-dimensional array of word lines, bit lines and memory cells. The memory cells are arranged in multiple vertically stacked layers. In some layers the memory cells are implemented as field-programmable write-once memory cells, and in other layers the memory cells are implemented as field-programmable re-writable memory cells. In this way, both re-writability and permanent data storage are provided in an inexpensive, single-chip solution. Additional types and numbers of types of memory cells can be used.

Multiple-mode memory and method for forming same

A semiconductor device contains a word line, a charge storage region located above the word line, an active layer located above the charge storage region, a patterned etch stop layer located above a first portion of the active layer, and bit lines located over a portion of the etch stop layer and over second portions of the active layer.

Inverted staggered thin film transistor with etch stop layer and method of making same

A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

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Fremont, CA, United States of America

Michael A Vyvoda