Semiconductor Components Industries, LLC

Michael A Stapleton

Paul Jay Harriman

Gang Chen

Benjamin M Rice

Kisun Lee

Christopher J Gass

Ole P Moyer

Gary Horst Loechelt

Yenting Wen

Xiaogang Feng

Weiyun Chen

Improved current doubling DC-DC converters having an efficient sleep mode. An illustrative converter embodiment includes: a transformer, first and second inductors coupled together at a first voltage output terminal, a reserve capacitor coupled to a second output voltage terminal, a primary switch array, a secondary switch array, and a controller. The first and second inductors each have a drive terminal coupled to a respective terminal of the transformer secondary. The primary switch array operates to convert an input voltage into forward voltage pulses and reverse voltage pulses on the transformer primary. The secondary switch array selectively couples the first inductor's drive terminal to either a charge terminal of the reserve capacitor or to the second voltage output terminal. The controller at least temporarily suspends operation of the primary switch array during a sleep mode, and uses the reserve capacitor to sustain a voltage at the first voltage output terminal.

Current doubling DC-DC converter with efficient sleep mode

An illustrative current-doubling DC-DC conversion method includes: converting an input voltage into forward voltage pulses and reverse voltage pulses on a primary of a transformer having a secondary coupled between a drive terminal of a first inductor and a drive terminal of a second inductor, the first and second inductors each having a common terminal coupled to a first output voltage terminal; selectively coupling the first inductor's drive terminal to a charge terminal of a reserve capacitor or to a second output voltage terminal, the first inductor's drive terminal being coupled to the charge terminal at least during the forward voltage pulses; selectively coupling the second inductor's drive terminal to the charge terminal of the reserve capacitor or to the second output voltage terminal, the second inductor's drive terminal being coupled to the charge terminal at least during the reverse voltage pulses; and concurrently coupling the drive terminals of the first and second inductors to the charge terminal to concurrently boost current flow through the first and second inductors in response to a load transient.

Fast response for current doubling DC-DC converter

In accordance with an embodiment, a converter includes a circuit and method for charging a bootstrap capacitor. The circuit monitors a voltage across the bootstrap capacitor and enables charging the bootstrap capacitor in response to the voltage across the bootstrap capacitor being less than a threshold voltage.

Converter including a bootstrap circuit and method

A semiconductor component and a method for manufacturing the semiconductor component. In accordance with an embodiment, the semiconductor component includes a plurality of stacked semiconductor chips mounted to a support structure, wherein one semiconductor chip has a side with a plurality of electrical contacts electrically coupled to conductive tabs of the support structure. An electrical connector electrically connects an electrical contact formed from a side opposite the side with the plurality of electrical contacts to a corresponding conductive tab. Another semiconductor chip is mounted to the electrical connector and electrical contacts formed from this semiconductor chip are electrically connected to corresponding conductive tabs of the support structure.

Semiconductor component and method of manufacture

A method for mitigating aliasing effects in a single phase power converter and mitigating aliasing effects and inhibiting thermal run-away in a multi-phase power converter at varying load transition rates. A single phase or multi-phase power converter having an on-time is provided and the frequency of the power converter is adjusted so that a load step period and the on time of the single phase power converter are in a temporal relationship. Alternatively, a load step rate is inhibited from locking onto a phase current of the single phase power converter by suspending an oscillator signal. In accordance with another alternative, a load step rate is inhibited from locking onto a phase current of the single phase power converter by suspending an oscillator signal and dithering an input signal to the oscillator.

Method for inhibiting thermal run-away

A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.

Method for manufacturing a semiconductor component and structure therefor

In accordance with an embodiment, a converter includes a circuit and method for scaling a drive signal. The converter determines the power at its input and scales a drive signal in accordance with the input power. In accordance with another embodiment the converter determines the power at its output and scales the drive signal in accordance with the output power.

Method for scaling a drive signal and circuit therefor

A method for method for inhibiting thermal run-away in a multi-phase power converter at varying load transition rates. A multi-phase power converter having an on-time is provided and the frequency of the multi-phase power converter is adjusted so that a load step period and the on time of the multi-phase power converter are in a temporal relationship. Alternatively, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal. In accordance with another alternative, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal and dithering an input signal to the oscillator.

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Scottsdale, AZ, United States of America

Michael A Stapleton