Broadcom Corporation

Michael A Sokol

Michael A Chang

Xi Chen

William Chien

Jason Fan

A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.

Method and apparatus for reducing clock speed and power consumption

A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

Method and apparatus of inter-chip bus shared by message passing and memory access

A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

A programmable LED display system is disclosed. The system includes a programmable controller; a driver operative to generate a control signal in response to a signal provided by the programmable controller; and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

Apparatus and method for displaying system state information

A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

Switch having virtual shared memory

A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Switch memory management using a linked list structure

A programmable LED display system is disclosed. The system includes a programmable controller, a driver operative to generate a control signal in response to a signal provided by the programmable controller, and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

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San Jose, CA, United States of America

Michael A Sokol