Intel Corporation

Other

Marvell International Limited

Intel Corpoartion

G & R Pharmaceuticals, LLC

Health Solutions, L.l.c.

Michael A Rothman

Vincent J Zimmer

Mark Doran

Mallik Bulusu

Robert Charles Swanson

Andrew J Fish

Palsamy Sakthikumar

Michael Kinney

Glenn J Hinton

Zijian You

Mahesh S Natu

Robert E Gough

Jiewen Yao

David C Estrada

Qian Ouyang

Jerry Zhao

Mohan J Kumar

Jian Jun Wang

David Kimbal Dorwin

Ping Wu

Giri P Mudusuru

Lee G Rosenbaum

Greg P McGrath

Andy Miga

Sarathy Jayakumar

Chao B Zhang

Leena K Puthiyedath

Nicholas J Adams

Robert Patrick Hale

Hua Zhou

Gundrala D Goud

Kevin Yufu Li

Xiaogang Gu

Yi Qian

Xiaohu Zhou

Guo Dong

Ming Kuang

Fujin Huang

Ned M Smith

Gilbert A Neiger

Efraim Rotem

Eliezer Weissmann

Paul S Diefenbaugh

Krishnakanth Venkata Sistla

Andrew V Anderson

Richard A Uhlig

Barnes Cooper

Murugasamy K Nachimuthu

Steven M Bennett

Blaise B Fanning

Arvind A Kumar

Rahul Khanna

Raj K Ramanujan

Jeremy J Shrall

H Peter Anvin

Guy M Therien

Howard C Herbert

Bin Xing

Erik C Cota-Robles

Qi Rong Wang

Sebastian Schoenberg

Daniel Nemiroff

Nathan Heldt-Sheller

Stalinselvaraj Jeyasingh

Anil Aggarwal

Carl M Ellison

Nimrod Diamant

Rajesh Sankaran Madukkarumukumana

Patrick G Kutch

Kushagra V Vaid

Andrew D Henroid

Jose Andy Vargas

Amber D Huffman

Moshe Maor

Sham M Datta

Yasser Rasheed

Gopinatth Selvaraje

Michael S Richmond

Shamanna M Datta

Neelam Chandwani

Robert Bruce Bahnsen

Dixon Newbold

Richard T Beckwith

Matthew D Wood

Carey W Smith

Mrigank Shekhar

Qin Long

Omer Levy

Alain Kägi

Caidong Song

Shaofan Li

Larry D Aaron, Jr

Whe-Yong Lo

Michael Heffernan

Jie Lin

John P Lambino

Greg L Miller

Matthew E Tolentino

Line Rothman

Xiaojian Wu

Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

Update of boot code handlers

Examples for transitioning between operating systems are disclosed. An example apparatus includes reserved copy circuitry to copy state data of a first operating system from a first portion of first memory to a second portion of the first memory in response to an operating system toggle event; toggle event circuitry to, in response to a determination that the state data has been copied to the second portion of the first memory, initiate execution of a second operating system, the second operating system loaded from a hibernation file in second memory; and write out circuitry to copy the state data of the first operating system from the second portion of the first memory to the hibernation file while the second operating system is executed on the apparatus.

Technologies for operating system transitions in multiple-operating-system environments

A disclosed example to protect memory from buffer overflow or underflow includes defining an implicit bound pointer based on an implicit bound pointer definition in a configuration file for a memory region; instrumenting object code with an implicit buffer bound check based on the implicit bound pointer; and generating hardened executable object code based on the object code, the implicit buffer bound check, and the implicit bound pointer, the implicit bound pointer located in the hardened executable object code during a compilation phase to facilitate loading the implicit bound pointer in a global bounds table during runtime for access by the implicit buffer bound check.

Methods and apparatus to protect memory from buffer overflow and/or underflow

In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Computing performance and power management with firmware performance data structure

Technologies for transitioning between operating systems include a computing device having a main memory and a data storage device. The computing device executes a first operating system and monitors for an operating system toggle event. The toggle event may be a software command, a hardware buttonpress, or other user command. In response to the toggle event, the computing device copies state data of the first operating system to a reserved memory area. After copying the state data, the computing device executes a second operating system. While the second operating system is executing, the computing device copies the state data of the first operating system from the reserved memory area to the data storage device. The computing device monitors for operating system toggle events during execution of the second operating system and may similarly toggle execution back to the first operating system. Other embodiments are described and claimed.

An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.

Low latency boot from zero-power state

An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

Dynamic timer adjustment to improve performance and inhibit livelock conditions

An embodiment of a semiconductor package apparatus may include technology to determine one or more filtered memory locations of a memory, determine if a read access for the memory corresponds to the one or more filtered memory locations, and return a pre-determined filter value as a result of the read access if the read access is determined to correspond to the one or more filtered memory locations. Other embodiments are disclosed and claimed.

On access memory zeroing

An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor coupled to secure non-volatile storage; and at least one storage medium having firmware instructions stored thereon for causing, during runtime and after an operating system for the apparatus has booted, the cryptoprocessor to (a) store a key within the secure non-volatile storage, (b) sign an object with the key, while the key is within the cryptoprocessor, to produce a signature, and (c) verify the signature. Other embodiments are described herein.

Management of authenticated variables

Methods, systems and storage media are disclosed for enhanced system boot processing that authenticates boot code based on biometric information of the user before loading the boot code to system memory. For at least some embodiments, the bio-metric authentication augments authentication of boot code based on a unique platform identifier. The enhanced boot code authentication occurs before loading of the operating system, and may be performed during a Unified Extensible Firmware Interface (UEFI) boot sequence. Other embodiments are described and claimed.

Anti-theft in firmware

The present application is directed to access isolation for multi-operating system devices. In general, a device may be configured using firmware to accommodate more than one operating system (OS) operating concurrently on the device or to transition from one OS to another. An access isolation module (AIM) in the firmware may determine a device equipment configuration and may partition the equipment for use by multiple operating systems. The AIM may disable OS-based equipment sensing and may allocate at least a portion of the equipment to each OS using customized tables. When transitioning between operating systems, the AIM may help to ensure that information from one OS is not accessible to others. For example, the AIM may detect when a foreground OS is to be replaced by a background OS, and may protect (e.g., lockout or encrypt) the files of the foreground OS prior to the background OS becoming active.

Access isolation for multi-operating system devices

In some embodiments, the invention involves partitioning resources of a manycore platform for simultaneous use by multiple clients, or adding/reducing capacity to a single client. Cores and resources are activated and assigned to a client environment by reprogramming the cores' route tables and source address decoders. Memory and I/O devices are partitioned and securely assigned to a core and/or a client environment. Instructions regarding allocation or reallocation of resources is received by an out-of-band processor having privileges to reprogram the chipsets and cores. Other embodiments are described and claimed.

System and method for supporting metered clients with manycore

A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.

Methods and apparatus to suspend and resume computing systems

A method for booting a data processing system (DPS) involves, during a boot process of the DPS, using a preliminary bootcode module from a low-speed nonvolatile memory (NVM) in the DPS to load a main bootcode module from a high-speed NVM in the DPS into a volatile random access memory (RAM) in the DPS, wherein the high-speed NVM supports a read speed that is faster than a maximum read speed of the low-speed NVM. The method also involves, during the boot process, after loading the main bootcode module from the high-speed NVM into the RAM, using the main bootcode module to boot the DPS to an operating system (OS). The method may also involve using the preliminary bootcode module to automatically determine whether the main bootcode module from the high-speed NVM has good integrity. Other embodiments are described and claimed.

Technology to facilitate rapid booting with high-speed and low-speed nonvolatile memory

Apparatuses, methods and storage medium associated with streamlined physical reset are described herein. In embodiments, an apparatus for computing, including streamlined physical reset, may comprise one or more processor cores; memory having a plurality of memory locations; and a basic input/output system (BIOS) to provide basic input/output system services, wherein the BIOS stays within a range of memory locations during each initialization of the BIOS, including an initialization of the BIOS that is part of a physical reset of the apparatus, to streamline the physical reset. Other embodiments may be described and/or claimed.

Streamlined physical restart of servers method and apparatus

Growing community of inventors

Puyallup, WA, United States of America

Michael A Rothman