International Business Machines Corporation

Marvell Asia Pte., Ltd.

Michael A Roberge

Darren Lane Anand

Minh H Tong

Eric D Hunt-Schroeder

Dale E Pontius

Endre P Thoma

Edward J Nowak

Kevin William Gorman

Francis H Chan

John A Gabric

John T Phan

Adrian J Paparelli

A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage Vfor a fuse programing period or a first non-zero intermediate voltage Vfor a non-fuse programming period.

Voltage power switch

Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.

Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method

Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Method and apparatus for DLL lock latency detection

An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.

Integrated circuit module having reduced impedance and method of providing the same

An off-chip driver (OCD) circuit including a clamp circuit to limit overdrive is provided. The circuit comprises an input signal which is inverted to provide an output signal. The driver circuit is comprised of a source-follower transistor to pull-down the output signal. The clamp circuit actively feeds back the source-follower potential to slow down the OCD and minimize ground bounce and noise that causes circuits to fail and signal integrity to be corrupted. The simple drive and clamp circuit is comprised of three transistors, one resistor, and one capacitor. The OCD slew rate is controlled by a current source and provides an output that changes between a positive voltage and ground. The circuit limits dv/dt without using a large resistor as a source follower, hence minimizing the adverse effect on performance.

Clamp circuit to limit overdrive of off chip driver

A noise detection and delay receiver circuit includes a circuit input and output and a plurality of individual receiver circuits connected to the input having trip points which range from a low trip point to a high trip point. Edge detect circuitry and delay circuitry are used to prevent the output from changing back to the previous state for a period of time immediately after it has just changed state. Multiple transitions of the input voltage across the trip points of the individual receivers are used to delay the response until noise has settled out of the input signal.

Growing community of inventors

Milton, VT, United States of America

Michael A Roberge