Intel Corporation

Nvidia Corporation

Other

Cray Incorporated

Michael A Parker

Thomas D Lovett

Albert S Cheng

Mario Flajslik

Eric R Borch

Steven Lee Scott

Wishwesh Anil Gandhi

Stephen William Keckler

Olivier Giroux

Debajit Bhattacharya

William James Dally

Mark Douglas Hummel

Alexander Lev Minkin

Robert L Alverson

Brucek Kurdo Khailany

Manan Patel

Robert Zak

Ravindra Babu Ganapathi

Ravi Murty

Vignesh Trichy Ravi

Timothy J Johnson

Srinivas Santosh Kumar Madugula

Scott S Diesing

Raghuram L

Ivan Tanasic

Francesc Guim Bernat

Shirish C Gadre

David Pardo Keppel

Richard J Dischler

Gary S Muntz

Mark S Birrittella

Laurence S Kaplan

Ronny Krashinsky

Wayne Alan Downer

James Robert Kohn

Raymond Hoi Man Wong

Eric P Lundberg

Gregory J Faanes

David Fontaine

Gaspar Mora Porta

Abdulla Bataineh

Timo Schneider

Roberto Penaranda Cebrian

Ze Long

Gregory J Hubbard

Kun Fang

Hemayet Hossain

Steven F Hoover

Evgeny Bolotin

Nan Ni

Gene Wu

Zvi Guz

Adwait Jog

Skef Iterum

Various embodiments include techniques for performing speculative remote memory operation tracking in a multiprocessor computing system. Conventionally, transfers of data between processors and other components of a computing system require memory synchronization operations to determine that the data is valid and coherent before the data is transferred from a destination to a requesting source. Existing techniques for performing these memory synchronization operations are increasingly inefficient as the number of components in a computing system increases, particularly for remote memory operations. The disclosed techniques track remote memory operations and speculatively perform these memory synchronization operations. As a result, a given memory synchronization operation is often complete prior to the corresponding remote memory operation arrives at the destination, leading to improved efficiency and performance of remote memory operations in complex computing systems.

Speculative remote memory operation tracking for efficient memory barrier

Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Self-synchronizing remote memory operations in a multiprocessor system

Various embodiments include techniques for performing memory operations in a computing system. A processing unit in the computing system performs memory operations by accessing memory using two concurrent memory address maps (AMAPs). The processing unit access memory via a first fine-grain distributed AMAP in order to access memory with high-bandwidth without imposing strict ordering of memory operations. The processing unit access memory via a second AMAP source-ordered non-distributed AMAP in order to access memory where memory synchronization latency is more important than memory bandwidth. By accessing memory via the two concurrent AMAPs, the processing unit can select between high-bandwidth memory access and source-ordered memory access interchangeably, depending on which is desired for each memory operation. Further, the fine-grain distributed AMAP and the source-ordered non-distributed AMAP can maintain synchronization and coherency between one another concurrently without software intervention, thereby alleviating the burden on the application programmer to manage the two AMAPs.

Simultaneous distributed and non-distributed address maps and routing protocols in a computing system

Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

Thread synchronization across memory synchronization domains

There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.

Fast data center congestion response based on QoS of VL

This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

Traffic class arbitration based on priority and bandwidth allocation

Technologies for improving throughput in a network include a node switch. The node switch is to obtain expected performance data indicative of an expected data transfer performance of the node switch. The node switch is also to obtain measured performance data indicative of a measured data transfer performance of the node switch, compare the measured performance data to the expected performance data to determine whether the measured data transfer performance satisfies the expected data transfer performance, determine, as a function of whether the measured data transfer performance satisfies the expected data transfer performance, whether to force a unit of data through a non-minimal path to a destination, and send, in response to a determination to force the unit of data to be sent through a non-minimal path, the unit of data to an output port of the node switch associated with the non-minimal path. Other embodiments are also described.

Technologies for selecting non-minimal paths and throttling port speeds to increase throughput in a network

Fast data center congestion response

Technologies for densely packaging network components for large scale indirect topologies include group of switches. The group of switches includes a stack of node switches that includes a first set of ports and a stack of global switches that includes a second set of ports. The stack of node switches are oriented orthogonally to the stack of global switches. Additionally, the first set of ports are oriented towards the second set of ports and the node switches are connected to the global switches through the first and second sets of ports. Other embodiments are also described and claimed.

Technologies for densely packaging network components for large scale indirect topologies

Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.

Technologies for ethernet gateway congestion management in high-performance computing architectures

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

System and method to enable fairness on multi-level arbitrations for switch architectures

Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.

Technologies for efficiently determining a root of congestion with a multi-stage network switch

Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.

Technologies for balancing throughput across input ports of a multi-stage network switch

Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.

Performance monitoring

Growing community of inventors

Santa Clara, CA, United States of America

Michael A Parker