Nvidia Corporation

Adobe, Inc.

Nvdia Corporation

New Microtime Inc.

Michael A Ogrinc

Duncan Andrew Riach

Stephen Donald Lew

Leslie E Neft

David Wyatt

Brett T Hannigan

Brijesh Tripathi

Tyvis Cheung

Wayne D Young

Wayne Douglas Young

Steven T Mayer

Stephen E Crane

Jonah Matthew Alben

John M Danskin

Robert Leyland

Anthony Michael Tamasi

Michael Shinsky

Robert L Lay

Gerald A Raitzer

Clifford Hersh

Mark S Krueger

Aron L Wong

Raymond Pon

John F Schlag

Sven Jensen

LeeAnn Heringer

Bradley G Stewart

Andrew E Wade

Robert A Card

Dhawal Kumar

Lawrence Stead

Daniel William Nolan

Brian C Knittel

Kevin M Collins

Ronda L Collier

Charles P Clarke

Chris R Burns

A method and system for detecting a display mode suitable for a reduced display refresh rate are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a memory and a processing unit. The memory stores multiple image surface data. The processing unit is configured to compose a first display frame from a first base surface and optionally a first overlay surface, calculate a first numerical code representative of a first frame content of the first display frame, compose a second display frame from a second base surface and optionally a second overlay surface, calculate a second numerical code representative of a second frame content of the second display frame, and track the results of comparing the first numerical code with the second numerical code to determine whether a change between the first frame content and the second frame content has occurred.

Method and system for detecting a display mode suitable for a reduced refresh rate

One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Multiple simultaneous unique outputs from a single display pipeline

One embodiment of the present invention sets forth a technique for controlling mode switches in hardware. The resource manager includes an 'is mode possible' function that evaluates a given mode in conjunction with the limitations of the hardware to determine if the given mode is feasible. The display driver is configured to call this function to validate a proposed mode before generating commands specifying the state changes for the display heads. The display software interface hardware module within the GPU processes these commands and follows a standard sequence of steps to implement the mode switch. The steps may include interrupts to the resource manager to re-validate the proposed mode, again calling the 'is mode possible' function, or perform operations that are not yet supported in the hardware. Advantageously, controlling mode switches in hardware enables less error-prone, more efficient, and more discerning mode switches relative to controlling mode switches in software.

System and method for controlling mode switches in hardware

A system, method, and computer program product are provided for determining a duty cycle for a pixel (e.g. of alternating pixel values to achieve an average pixel color). In use, a first value of a sub-color component bit of a pixel is determined. Additionally, a second value for the sub-color component bit of the pixel is calculated. Further, a duty cycle for alternating between the first value and the second value is determined (e.g. which when applied at normal display frame rate may achieve an average color).

System, method, and computer program product for determining a duty cycle for a pixel

A method and system are implemented to dynamically control a display refresh rate. Specifically, one embodiment of the present invention sets forth a method, which comprises the steps of driving a display device at a first refresh rate over a period of time, measuring a number of first content frames with changes in content out of a plurality of content frames that are generated over the period of time for the display device, and driving the display device at a second refresh rate if the number of the first content frames meets a first condition associated with a first threshold reference, and optionally driving the display device at a third refresh rate if the number of first content frames meets a second condition associated with a second threshold reference.

Method and system for dynamically controlling a display refresh rate

Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Backlight dimming and LCD amplitude boost

A display refresh system, method and computer program product are provided. In use, a refresh rate is adjusted for power saving purposes, and/or any other purpose(s) for that matter. Further, various embodiments are provided for reducing visual manifestations associated with a transition between a first refresh rate and a second refresh rate.

System, method and computer program product for adjusting a refresh rate of a display for power savings

One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Active raster composition and error checking in hardware

A method and system are implemented to measure quantitative changes in display frame content for dynamically controlling a display refresh rate. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of composing a first display frame from a first set of rendered image surfaces, composing a second display frame from a second set of rendered image surfaces, dividing the first display frame and the second display frame into a same number of frame regions. Also, for each of the frame regions, the method also includes the steps of calculating a first set of numerical codes and a second set of numerical codes representative of the content associated with the frame region in the first and second display frame, respectively; and determining an amount of changes in content between the first display frame and the second display frame based on the results of comparing the first set of numerical codes against the second set of numerical code.

Method and system of measuring quantitative changes in display frame content for dynamically controlling a display refresh rate

Embodiments of the present invention generally provide methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Backlight dimming  and LCD amplitude boost

One embodiment of the present invention sets forth a protocol for packing and transferring pixel data between integrated circuits. The data transfer protocol may be used between a graphics processing unit and a video output encoder unit. The data transfers may include up to 20 pixels per arbitration cycle. By packing pixel data for transfer over a bus with a relatively small set of output pins, overall package pin count is reduced, while maintaining sufficient bandwidth to carry the pixel data the output pins. By moving the analog circuitry to a separate device, linked to the GPU via the bus, noise from the GPU may be effectively mitigate through physical separation.

Bus protocol for transferring pixel data between chips

Growing community of inventors

San Francisco, CA, United States of America

Michael A Ogrinc