Mosel Vitelic Corporation

Promos Technologies, Inc

Mosel Vitalic Corporation

Michael A Murray

Li-Chun Li

Lawrence C Liu

Steve Eaton

Jon Allan Faue

Hsing Ti Tuan

Jinyong Chung

A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM

A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Memory refresh methods and circuits

A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

DRAM with edge sense amplifiers which are activated along with sense

In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

Dram with new I/O data path configuration

An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

I/O bias circuit insensitive to inadvertent power supply variations for

A semiconductor device disables itself during power-up until the internal power supply voltage and other circuits reach states in which the device can operate properly. The internal power supply voltage is coupled to the input terminal of an inverter through a delay network. During power-up, the device remains disabled until the voltage at the input terminal of the inverter reaches the inverter trip point. The delay network and the inverter are designed so that the voltage at the inverter's input terminal does not reach the inverter trip point until the internal power supply voltage and other circuits have reached states in which the device can operate properly. When the (device is turned off, the inverter input terminal is discharged quickly by a diode or resistor. Therefore, if the power is turned back on immediately, a suitable delay will be provided.

Using the internal supply voltage ramp rate to prevent premature

A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude. The intermediate value reduces the likelihood of latch-up during power-up, but the intermediate value does not go beyond the target value thus does not create a significant pn-junction current leakage in semiconductor regions to which the bias voltage is applied.

Generation of signals from other signals that take time to develop on

A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

Space saving laser programmable fuse layout

An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the intermediate node by means of a power bus formed as part of the chip interconnect structure, power is supplied to an external wire which is coupled from the supply to the intermediate node. Other than as connected to the supply node and intermediate node, the wire is electrically isolated from the die. This structure and method for making the semiconductor package allow power to be distributed within a semiconductor chip without sacrificing valuable chip space and without requiring a special lead frame for distributing the power within the semiconductor chip.

Intrachip power distribution package and method for semiconductors

A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

Reconfigurable multiplexed address scheme for asymmetrically addressed

The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

Simulated DRAM memory bit line/bit line for circuit timing and voltage

DRAM with new I/O data path configuration

A sense amplifier charging circuit can work with different power supply voltages (EVCC). When EVCC is high, a signal generated from EVCC disables some of the charging transistors to reduce the circuit noise. When EVCC is low, the signal generated from EVCC enables the transistors thus increasing the circuit speed.

Charging a sense amplifier

A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

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Bellevue, WA, United States of America

Michael A Murray