Freescale Semiconductor,inc.

Motorola Corporation

University of Illinois

Michael A Mendicino

Byoung W Min

Hector Adrian Sanchez

Kathleen C Yu

Perry H Pelley

Troy L Cooper

Laegu Kang

Jian Feng Chen

Mariam G Sadaka

Venkat Kolagunta

Vance H Adams

Choh-Fei Yeap

Edmund G Seebauer

A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region.

Isolation trench processing for strain control

A semiconductor topography () is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line () arranged within an insulating layer () of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line () within an insulating layer () arranged above a wafer substrate () and forming a silicon layer () upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate () upon an SOI substrate having a conductive line () embedded therein and implanting dopants within the semiconductor topography to form source and drain regions () within an upper semiconductor layer () of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Embedded substrate interconnect for underside contact to source and drain regions

A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.

Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof

A semiconductor () has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (), that are connected by a via or conductive region () and interconnect (). The via or conductive region () contacts a bottom surface of a diffusion or source region () of the transistor and contacts a first () of the capacitor electrodes. A laterally positioned vertical via () and interconnect () contacts a second () of the capacitor electrodes. A metal interconnect or conductive material () may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element

Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region

Method for forming a semiconductor device having electrical contact from opposite sides

An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Body-tied silicon on insulator semiconductor device and method therefor

Method of forming body-tied silicon on insulator semiconductor device

A trench (,) for isolation is formed in a substrate (,) through an opening in a nitride masking layer (,). After the trench is formed, the opening in the nitride masking layer is widened uniformly by an isotropic etch (FIG.,). This leaves the nitride masking layer uniformly recessed from the edge of the trench. The trench is then filled with oxide and, with CMP, is etched back so that there is a nearly planar surface with oxide (,) extending outside the trench wall along the surface and abutting the recessed nitride masking layer (,). The nitride masking layer is then removed so that there is left an oxide overlap portion (,) which extends outside the trench wall. Subsequent oxide etches which are required for formation of transistors etch the oxide overlap portion instead of etching down into the oxide along the sidewall of the trench whereby an improved device is formed.

Method for preventing trench fill erosion

The present invention concerns a completely selective and efficient method for chemical vapor deposition of titanium disilicide onto silicon regions of a silicon substrate including silicon dioxide regions. According to the method of the present invention a silicon substrate is heated to a low temperature. Silicon nucleation is induced by the introduction of a silicon precursor, such as silane. Silicon nucleates primarily on the silicon regions, with minimal nucleation on silicon dioxide regions. The silicon nuclei are then converted to titanium disilicide by the low pressure introduction of titanium tetrachloride with or without continued supply of silane. Etching, preferably using chlorine gas, is used to remove the titanium disilicide formed from conversion. The etching leaves the silicon dioxide regions completely intact, while the silicon region is slightly textured. Steady state growth is then induced on the silicon region with complete selectivity by the introduction of silane and titanium tetrachloride under low pressure and temperature conditions. During the steady state growth minimal silicon is consumed from the underlying silicon region.

Growing community of inventors

Austin, TX, United States of America

Michael A Mendicino