Sigmatel, Inc.

Advanced Micro Devices Corporation

Integrated Device Technology, Inc.

Dallas Semiconductor Corporation

Michael A Margules

H Spence Jackson

Timothy W Markison

Mathew A Rybicki

Gregg S Kodra

Gerald Robert Talbot

Milam Paraschou

Edoardo Prete

Thomas H Likens, Iii

Balwinder Singh

Harry S Jackson

Alushulla Jack Ambundo

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

Low power VTT generation mechanism for receiver termination

A method and apparatus for recovering data by a digital audio interface begins by receiving a stream of biphase encoded data. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Data recovery method and module

A method and apparatus for recovering data by a digital audio interface, where the data may be transmitted over a single transmission path in accordance with the AES3-1992 standard, begins by receiving a stream of biphase encoded data. The biphase encoded data is organized as a series of data block that each include a plurality of frames. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. In other words, the transitions of the data within the frame are occurring at the data rate. (Note that biphase encoding encodes a logic zero as no transition during a clock interval, encodes a logic one as a transition during a clock interval, and provides a transition at the next clock interval to indicate a new bit). If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. For example, when the next transition occurs during the first time window, the transition is representative of a logic one, where the subsequent transition corresponds to the beginning of the next bit. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Method and apparatus for data recovery

A method and apparatus for pulse position modulation begins when a digital data stream is received. The encoding process continues by obtaining a set of bits from the digital data stream and modulating the set of bits into a pulse having a pulse width. Next, a transition edge of the pulse is positioned at one of a plurality of time intervals within a time chip based on the set of bits, wherein the pulse width is greater than each of the plurality of time intervals.

Method and apparatus for pulse position modulation

A method and apparatus for encoding data into a pulse pattern begins by encoding header data based on a first pulse encoding convention to produce a header pulse pattern. The resulting header pulse pattern occupies multiple time chips and indicates that subsequent pulse pattern signals are valid. After generating the header pulse pattern, a set of bits of a stream of data is encoded based on a second pulse encoding convention to produce a data pulse pattern. The data pulse pattern occupies at least one time chip. The first and second encoding conventions are used to ensure that the header data and data are encoded in distinguishing manners such that both can be accurately decoded. Such conventions include using a predetermined pulse pattern to represent the header data, which is only used for the header data.

Method and apparatus for pulse pattern modulation

A method and apparatus for pulse position demodulation begins by receiving a pulse that is positioned approximately at one of a plurality of time intervals within a time chip, where the pulse has a pulse width that is greater than each of the plurality of time intervals. The decoding process then continues by determining the time interval in which a transition edge of the pulse lies. From the particular time interval, a set of bits is determined.

Method and apparatus of pulse position demodulation

A method and apparatus for converting a digital signal into an analog signal with minimal self generated noise is achieved by a digital to analog converter that includes a current source, a switch circuit, and a gating circuit. The current source provides a current, which is representative of digital data, to the switch circuit. The switch circuit, based on control signals provided by the gating circuit, routes the current to an analog node and/or a reference potential node. The control signals cause the switch circuit to route the current to both nodes when a clock pulse signal is in a first state regardless of the state of the data, to route the current to the analog node when the clock pulse signal is in a second state and digital data is in a second state, and to route the current to the reference potential node when the clock pulse signal is in the second state and the digital data is in a first state. In this manner, an analog representation of the digital data is present at the analog node.

Method and apparatus for digital to analog conversion

A method and apparatus for an oversampled single bit digital to analog convertor (DAC) is accomplished by using an FIR filter as the analog reconstruction filter, wherein the FIR filter includes primary current sourcing circuitry and secondary current sourcing circuitry. The primary current sourcing circuitry is used to produce a portion of the FIR coefficients having relatively large values, while the secondary current sourcing circuitry is used to fine tune the FIR coefficients having the relatively large values and to produce the other FIR coefficients. Combining the results of the primary current sourcing circuitry and the secondary current sourcing circuitry produces an analog signal.

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Austin, TX, United States of America

Michael A Margules