Texas Instruments Corporation

Hitachi, Ltd.

Michael A Lamson

Katherine G Heinen

Gen Murakami

Ichiro Anjoh

Navinchandra Kalidas

Heping Yue

Siva Prakash Gurrum

Darvin R Edwards

Rajiv Carl Dunne

Homer B Klonis

Howard Raeburn Test

Roger J Stierman

Nozar Hassanzadeh

Richard D James

Jay Michael Lawyer

Subhendu Kundu

Ramani Ramesh

Truong Ho

Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Coaxial four-point probe for low resistance measurements

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.

Structure and method of high performance two layer ball grid array substrate

A semiconductor device has a semiconductor chip with a periphery and an IC organized in a core portion and a peripheral portion. The IC has a top level of interconnecting metal traces () from the peripheral portion to the core portion; the traces are covered by an insulating overcoat () which has peripheral windows to expose bond pads. The circuit further has at least one level of metal lines () on top of the insulating overcoat; the lines lead from the chip periphery towards the chip core, wherein each line () is substantially parallel to one of the traces () underneath the insulating overcoat and vertically aligned therewith. After assembling the chip onto a leadframe with segments (), bonding wires () connect the bond pads () and the metal lines () with the segments.

Wire bonded semiconductor device having low inductance and noise

A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning the wires with a low modulus sheath, and by protecting chip bond pad metallization 

Low capacitance coupling wire bonded semiconductor device

In a method and system for testing a test sample (), a simulation program () is used to augment test results provided by a legacy test system (). The legacy test system () includes a measuring device () providing a test input () to the test sample () and receiving a test output () from the test sample () in response to the test input (). The simulation program () simulates the test sample () by predicting a simulated output () of the test sample () in response to receiving a simulated input (). A plurality of simulated failures is simulated in the simulation program (), with each simulated failure generating a corresponding simulated output. The simulation program () includes a model () for the measuring device (), the model () providing the simulated input (). A comparator () compares the test output () with the simulated output () to determine a match. The simulated failure providing the match is used to predict a predicted failure location within the test sample ().

FA tool using conductor model

A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.

Semiconductor package with conductor impedance selected during assembly

A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning, the wires with a low modulus sheath, and by protecting chip bond pad metallization.

According to the electrical modeling system and method provided by the present invention, the electronic structure to be modeled is segmented into an ordered sequence of segments, each segment is electrically analyzed individually, and the resulting data is collated, or integrated back again whereby the model output is preferably created in a format generally suitable for electrical models of integrated circuits. Examples of electronic structures which can be modeled by the system and method of the invention include leadframes, packages, complete devices, and electronic devices assembled on motherboards.

System for electrically modeling an electronic structure and method of operation

An electrical connection web, operable at high frequency and configured on a dielectric substrate, comprising a plurality of generally parallel signal lines having graduated width and variable spacings, and said widths and spacings cooperatively selected such that the characteristic impedance of said signal lines is approximately the same for each line of said plurality and approximately constant over the length of each said signal line, whereby signal integrity for each said line is enhanced and cross talk between said lines is reduced.

Constant impedance routing for high performance integrated circuit packaging

A semiconductor package substrate for assembling an integrated circuit chip operable at fast ramp rate signals and clock rates, comprising an insulating support having a region for attaching said chip; a pattern of electrical interconnections, disposed on said substrate in one metallization level and operable for transmitting waveforms; and a low pass filter for removing unwanted high frequency components from said transmitted waveforms, comprising a network of inductors and capacitors formed within said one metallization level and positioned substantially within said substrate region for chip attachment.

Low pass filter integral with semiconductor package

An integrated circuit chip package is provided which incorporates one or more differential pairs of signal lines coupled to an integrated circuit chip. The differential pairs each include a first signal line and a second signal line. The first signal lines are non-coplanar with the second signal lines. The first signal lines of the differential pairs may be provided in a first plane. The second signal lines of the differential pairs may be provided in a second plane different from the first plane. A first ground plane is provided adjacent the first signal lines and a second ground plane is provided adjacent the second signal lines. The spacing of respective signal lines provides, among other things, the capability of having a greater density of differential pairs of signal lines within the planar area of an integrated circuit chip package.

Growing community of inventors

Westminster, TX, United States of America

Michael A Lamson