Intel Corporation

Carnegie Mellon University

Michael A Kozuch

Gilbert A Neiger

Richard A Uhlig

Alain Kagi

Stalinselvaraj Jeyasingh

Erik C Cota-Robles

Sebastian Schoenberg

Stephen T Chou

David W Grawrock

James A Sutton, Ii

Lawrence O Smith

Andy Glew

Andrew V Anderson

Steven M Bennett

Clifford D Hall

Steve M Bennett

Hong Wang

Andrew F Glew

David I Poisner

Konrad K Lai

Dion Rodgers

Ralph Michael Kling

Robert T George

Bradley Gene Burgess

Fernando C M Martins

Yong-fong Lee

Erich Boleyn

David A Berson

Eric C Cota-Robles

Scott Dion Rodgers

Xiang Chris Zou

Anshul Gandhi

Larry O Smith

Mor Harchol-Balter

Varun Gupta

Stalinselvaraj Jevasingh

A dynamic capacity management policy for multi-paralleled computing resources (e.g., application servers, virtual application servers, etc.) that includes one or more of a state-change component, a load-balancing component, and a robustness-control component. The state-change component delays the release (e.g., powering down of a physical server, removal from a virtual-server lease, etc.) of each computing resource for a set amount of time. The load-balancing component can work in conjunction with the state-change component to reduce the number of idle computing resources by distributing incoming requests in a manner that keeps the already-processing computing resources as full of requests as possible. The robustness-control component scales capacity as a function of the current number of requests within the system of computing resources to account for variations other than request rate, such as request size, reduced processor frequency, network slowdowns, etc., that affect processing capacity.

Dynamic capacity management of multiple parallel-connected computing resources

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Invalidating translation lookaside buffer entries in a virtual machine system

A method and system for supporting personal computing in a public computing infrastructure. The system includes a plurality of computers to be used by patrons of the public computing infrastructure. The system includes a server coupled to the plurality of computers via a network connection. Each of the plurality of computers includes a virtual machine monitor, which includes a plurality of base virtual machine images. Each of the base virtual machine images is customized for a particular hardware and software configuration representing a specific computing environment. The virtual machine monitor launches one of the plurality of base virtual machine images, arbitrates access to system resources via the launched virtual machine image, stores the changes in the state of the virtual machine image when a user terminates a session, and returns a computer to an appropriate state to enable the user to resume the terminated session in subsequent sessions.

Support for personal computing in a public computing infrastructure by using a single VM delta image for each VM base image utilized by a user

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of () a possibly empty set of operations that invalidate a variable number of TLB entries, () a possibly empty set of operations that invalidate exactly one TLB entry, () a possibly empty set of operations that invalidate the plurality of TLB entries, () a possibly empty set of operations that enable and disable use of virtual memory, and () a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Invalidating translation lookaside buffer entries in a virtual machine (VM) system

An article of manufacture is provided for securing a region in a memory of a computer. According to one embodiment, the article of manufacture comprises a machine-accessible medium including data that, when accessed by a machine, causes the machine to: halt all but one of a plurality of processing elements in a computer, where the halted processing elements enter into a special halted state; load content into the region only after the halting of all but the one of the plurality of processing elements and the region is protected from access by the halted processing elements; place the non-halted processing element into a known privileged state; and cause the halted processing elements to exit the halted state after the non-halted processing element has been placed into the known privileged state.

Method and apparatus for loading a trustable operating system

A method and apparatus is provided for securing a region in a memory of a computer. According to one embodiment, the method comprises halting of all but one of a plurality of processors in a computer. The halted processors entering into a special halted state. Content is loaded into the region only after the halting of all but the one of the plurality of processors and the region is protected from access by the halted processors. The method further comprises placing the non-halted processor into a known privileged state, and causing the halted processors to exit the halted state after the non-halted processor has been placed into the known privileged state.

A method and system for support of personal computing in a public computing infrastructure. The system including a plurality of computers to be used by patrons of a public computing infrastructure. The system also includes one or more servers coupled to the plurality of computers via a network connection. Each of the plurality of computers includes a virtual machine monitor. The virtual machine monitor has a plurality of base virtual machine images, each of the base virtual machine images is customized for a particular hardware and software configuration representing a specific computing environment. The virtual machine monitor launches one of the plurality of base virtual machine images, arbitrates access to system resources via the launched virtual machine image, stores the changes in the state of the virtual machine image when a user terminates a session, and returns a computer to an appropriate state to enable the user to resume the terminated session in subsequent sessions.

An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment

In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.

System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time

In one embodiment, a processor mode is provided for guest software. The processor mode enables the guest software to operate at a privilege level intended by the guest software. When the guest software attempts to perform an operation restricted by the processor mode, the processor mode is exited to transfer control over the operation to a virtual-machine monitor, which runs outside this processor mode.

Processor mode for limiting the operation of guest software running on a virtual machine supported by a virtual machine monitor

Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.

Methods and systems to manage machine state in virtual machine operations

A method and apparatus is provided in which a trustable operating system is loaded into a region in memory. A start secure operation (SSO) triggers a join secure operation (JSO) to halt all but one central processing unit (CPU) in a multi-processor computer. The SSO causes the active CPU to load a component of an operating system into a specified region in memory, register the identity of the loaded operating system by recording a cryptographic hash of the contents of the specified region in memory, begin executing at a known entry point in the specified region and trigger the JSO to cause the halted CPUs to do the same.

A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

Identifying and processing essential and non-essential code separately

Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.

Growing community of inventors

Beaverton, OR, United States of America

Michael A Kozuch