Infineon Technologies Ag

International Business Machines Corporation

Siemens Aktiengesellschaft

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Qimonda North America Corporation

Michael A Killian

Thomas Vogelsang

Christopher P Miller

Mark David Jacunski

William R Tonti

Martin Brox

Helmut Schneider

Michael Dieter Richter

Russell J Houghton

Wolfgang Hokenmaier

Martin Versen

Ciaran J Brennan

Josef Schnell

Duane E Galbi

Nicholas Martin Van Heel

Adam B Wilson

Oliver Kiehl

Andre Sturm

Klaus J Lau

Grant McNeil

Jochen Hoffman

Fergal Bonner

Zach Johnson

Changduk Kim

A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

Reducing leakage current in memory device using bitline isolation

Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.

Programmable sense amplifier multiplexer circuit with dynamic latching mode

A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.

Edge pad architecture for semiconductor memory

A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Test mode for IPP current measurement for wordline defect detection

Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the latch circuit in a first state when the fuse is in a first condition and keeps the latch circuit unchanged when the fuse is in a second condition. While the first signal is being supplied, a second signal is supplied to the latch circuit that keeps the latch circuit in the first state when the fuse is in the first condition and sets the latch circuit in a second state when the fuse is in the second condition.

Fuse latch circuit with non-disruptive re-interrogation

A pre-charge circuit for a memory device having a sense amplifier shared between right and left banks of memory cells and a method of pre-charging the shared sense amplifier. The circuit is operated according to the method of the invention such that the sense amplifier is always pre-charged from the side that was previously active. The circuit includes right and left bank isolation transistor pairs connected between the shared sense amplifiers and the right and left banks. The isolation transistor pairs are controlled by a flip flop having a left bank state and a right bank state and complementary left and right outputs that turn off the left isolation transistor pair and turn on the right pair during row operations to the right and vice-versa. The flip-flop is kept in the right bank state after a row operation to the right bank so that the sense amplifier is pre-charged from the right after row operations to the right and the flip-flop is kept in the left bank state after a row operation to the left so that the sense amplifier is pre-charged from the left after row operations to the left.

Pre-charge circuit and method for memory devices with shared sense amplifiers

The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate. The electrical isolation surrounding the well includes (1) a second-type dopant isolation regions in a first type substrate surrounding and abutting the well, (2) a substrate doped with second type doping, and (3) dielectric isolation, such as deep trench, STI, and buried oxide layer. The well may be isolated by any of these methods separately or in combination.

Isolated well ESD device

A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a 'noise killer' at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.

Configuration for crosstalk attenuation in word lines of DRAM circuits

An interleaved sense amplifier with a single sided precharge device which provides simplification of the conventional sense amplifier circuitry, as well as a reduction in the area occupied by the sense amplifier circuitry, thereby resulting in chip size reduction. A precharge device is placed on only one side of the sense amplifier, which is used to charge both sets of bit lines pairs that are coupled to the sense amplifier to a common voltage during an equalization/precharge operation. In addition, the resistance of the transistors comprising the precharge device is increased such that the precharge transistors can be further utilized for limiting the flow of current between the bit line pair and precharge net, which obviates the need for the additional leakage limiter devices in the conventional sense amplifier arrangement. Thus, a compact and simplified sense amplifier architecture is realized.

Interleaved sense amplifier with a single-sided precharge device

A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Decoded-source sense amplifier with special column select driver voltage

An off-chip driver with regulated supplies compensates for power supply fluctuations. The circuit reduces di/dt noise by providing complementary voltage regulators to regulate the high and low supplies to the driver stages such that they see a constant operating voltage regardless of changes in supply voltage, V.sub.CC. The circuit uses two push-pull stages which charge and discharge the output load capacitance, C.sub.0. This regulated voltage to the driver stages reduces di/dt noise and provides a constant overdrive voltage, constant gate slew rate, and constant staging delay over a specified external supply voltage range.

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Richmond, VT, United States of America

Michael A Killian