Broadbus Technologies, Inc.

Michael A Kahn

Francis J Stifter, Jr

Matthew Sargeant

Catherine A Yadlon

Robert G Scheffler

Jason P Colangelo

Frank J Stifter

A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Data access and multi-chip controller

A system includes multiple input ports that forward received data (e.g., data packets) to each of multiple queues. Data received at the input ports of the system can be somewhat random or 'bursty' at times. That is, the input ports can receive data at a variable bit rate or unspecified bit rate from an internal system source or an external source such as an FTP (File Transfer Protocol) server or SCSI disk array. The queues output data at a constant bit rate. A two-dimensional scheduler associated with the system forces random inbound server traffic from the input ports to adhere to a QoS (Quality of Service) agreement such that the random nature of the inbound traffic does not negatively affect the deterministic guarantees of existing server traffic output from the queues. In other words, techniques herein ensure adherence to QoS requirements among the data flows, without overflowing the queues.

Methods and system to manage data traffic

An on-demand server system herein includes a memory controller that coordinates access to one or more flash-based memory devices. The flash devices store large amounts of video content that can be selectively viewed on-demand by each of multiple destinations over a respective network. In addition to having access to an array of flash memory devices, the memory controller has access to a corresponding read buffer and write buffer. Use of the read buffer and the write buffer enable the memory controller to switch between transferring data stored in the write buffer to the array of memory devices and transferring the data in the array of memory devices to the read buffer. The write buffer stores on-demand video content that can be selected for viewing by different users. The read buffer stores segments of the on-demand video content currently streamed to the users.

Data distribution and buffering

A low-latency storage memory system is built from multiple memory units such as high-density random access memory. Multiple access ports provide access to memory units and send the resultant data out interface ports. The memory units communicate with the access ports through an interconnected mesh to allow any access port to access any memory unit. An address virtualization mechanism using address translators allows any access port of the memory storage system to access requested data as abstract objects without regard for the physical memory unit that the data is located in, or the absolute memory addresses within that memory unit.

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Hudson, MA, United States of America

Michael A Kahn