International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Zeon Corporation

Elpis Technologies Inc.

Other

Applied Materials, Inc.

Jsr Corporation

Globalfoundries U.S. 2 LLC

Toshiba America Electronic Components, Inc.

Glogalfoundries, Inc.

Michael A Guillorn

Josephine B Chang

Isaac Lauer

Jeffrey W Sleight

Hsinyu Tsai

Paul S Chang

Xin Miao

Chi-Chun Liu

Bruce Bennett Doris

Nicolas J Loubet

Chung-Hsun Lin

Markus Brink

Guy M Cohen

Reinaldo Ariel Vega

Robert Russell Robison

Derren Neylon Dunn

Fei Liu

Kafai Lai

Joy Cheng

Karthik Balakrishnan

Terence B Hook

Eric Andrew Joseph

Hiroyuki Miyazoe

Gen Pei Lauer

Leland Chang

Jing Sha

Adam M Pyzyna

Sebastian Ulrich Engelmann

Alexander Reznicek

Pouya Hashemi

Ruqiang Bao

Tenko Yamashita

Zhen Zhang

Rajasekhar Venigalla

Kangguo Cheng

Balasubramanian Pranatharthiharan

Alfred Grill

Christian Lavoie

Amlan Majumdar

Shawn Peter Fetterolf

Daniel A Corliss

Satyavolu S Papa Rao

Jed Walter Pitera

Shogo Mochizuki

Vijay Narayanan

Cyril Cabral, Jr

Katherine Lynn Saenger

Wilfried Haensch

Damon B Farmer

George Stojan Tulevski

Chun Wing Yeung

Nicholas C M Fuller

Martin Glodde

Nicholas C Fuller

Martin Burkhardt

Effendi Leobandung

Ghavam G Shahidi

Stephen W Bedell

Steven J Holmes

Ying Di Zhang

Joshua T Smith

Eugene John O'Sullivan

Martin Michael Frank

Masahiro Nakamura

Conal Eugene Murray

Daniel Sanders

Muthumanickam Sankarapandian

Sarunya Bangsaruntip

Leathen Shi

Yann A Astier

Lidija Sekaric

Jingwei Bai

Balasubramanian S Pranatharthi Haran

Gurpreet Singh

Szu-Lin Cheng

Alexander M Friz

Wilfried Ernst-August Haensch

Philip S Waggoner

Edward J Nowak

Brent A Anderson

Dechao Guo

Keith Kwong Hon Wong

Andres Bryant

Bin Yang

Praneet Adusumilli

Michael Patrick Chudzik

Matthew Earl Colburn

Shreesh Narasimha

Steven John Koester

Dongbing Shao

Mahadevaiyer Krishnan

Alessandro Cesare Callegari

Michael F Lofaro

Katherina E Babich

Mark Hoinkis

Michael Joseph Rooks

Daniel James Dechene

Mickey H Yu

Tomohisa Konno

Tatsuya Yamanaka

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Gate-all-around field effect transistor having multiple threshold voltages

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

Nanosheet field effect transistors with partial inside spacers

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Electrical mask validation

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.

Trigate device with full silicided epi-less source/drain for high density access transistor applications

Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS

A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

Field effect transistor structures

A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

Automatic generation of via patterns with coordinate-based recurrent neural network (RNN)

A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.

Reducing chemoepitaxy directed self-assembled defects

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moir&#xe9; pattern.

Semiconductor structure for optical validation

A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Nanosheet and nanowire MOSFET with sharp source/drain junction

A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

High density programmable e-fuse co-integrated with vertical FETs

Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.

Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices

A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Generative adversarial networks for generating physical design layout patterns of integrated multi-layers

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Yorktown Heights, NY, United States of America

Michael A Guillorn