Intel Corporation

Other

Michael A Goldsmith

Uday R Savagaonkar

Carlos V Rozas

Francis X Mckeen

Vincent R Scarlata

Simon P Johnson

Ittai Anati

Gilbert A Neiger

Vedvyas Shanbhogue

Wesley Hamilton Smith

Ilya Alexandrovich

Rebekah M Leslie-Hurd

Siddhartha Chhabra

Prashant Dewan

Barry E Huntley

Alex Berenzon

David M Durham

Kiran S Panesar

Raghunandan Makaram

Amy L Santoni

Krystof C Zmudzinski

Stalinselvaraj Jeyasingh

John I Garney

Ernie F Brickell

Howard C Herbert

Gary L Graunke

Dion Rodgers

Philip R Lantz

Shlomo Raikin

Stephen R Van Doren

Gideon Gerzon

David J Cowperthwaite

Joseph Frank Cihula

Francis McKeen

Bernard Lint

Asher M Altman

Stephen J Tolopka

Gur Hildesheim

Don Alan Van Dyke

Jiang Tao Li

Rebekah Leslie

William Colin Wood

Scott Dion Rodgers

Jason Martin

Rinat Rappoport

Xiaozhu Kang

Paul S Schmitz

Anton Ivanov

Barrey E Huntley

Elizabeth Ann Goldsmith

Balaji Vembu

Ravi L Sahita

Shay Gueron

Andrew V Anderson

Richard A Uhlig

Geoffrey S Strongin

Steven M Bennett

Karanvir S Grewal

Scott R Janus

Sanjay Kumar

Erik C Cota-Robles

Sebastian Schoenberg

Xiaoning Li

Hisham Shafi

Ben S Wymore

Alain Kägi

Cory W Cox

Dewan Prashant

Alpha T Narendra Trivedi

A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Supporting secure memory intent

A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

System and method for one step address translation of graphics addresses in virtualization

A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

Method and apparatus to provide secure application execution

Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Instructions and logic to provide advanced paging capabilities for secure enclave page caches

Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.

Memory management in secure enclaves

Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

Virtual memory address range register

A protected graphics module can send its output to a display engine securely. Secure communications with the display can provide a level of confidentiality of content generated by protected graphics modules against software and hardware attacks.

Secure rendering of display surfaces

Growing community of inventors

Portland, OR, United States of America

Michael A Goldsmith