Google Inc.

Other

Michael A Glover

Nils Krahnstoever

Thomas DeWeese

Harold Jason Schiller

Carlo Contavalli

Michael Todd Joseph

Systems and methods for generating a master video stream from at least two live video streams are provided in this disclosure. The systems include a combination component that combines the live video streams to generate the master video stream. In one aspect, the live video streams can be copies of the same recording that are multicast from different locations according to User Datagram Protocol. The live video streams suffer different errors, such as stream corruption or stream error, due to the transmission. The combination component eliminates the errors in the live video streams due to transmission and creates a substantially error-free master video stream.

System, apparatus and method to facilitate live video streaming

A system and method for processing multicast streams is disclosed. A router receives the multicast streams and communicates the streams via communication tunnels to a set of ingestion pipelines. Each communication tunnel can be terminated upon the ingestion pipeline receiving a multicast stream. The set of ingestion pipelines process and deliver the multicast streams across existing IP infrastructure for real time distribution.

Multicast group ingestion

A parallel processor adapted to be used as a vector co-processor to a host computer, comprising a plurality of 1-bit processing elements (PEs) and an associated rapidly accessed memory and lateral data path switch providing rapid computational processing of data contained within contiguous bit locations of each 1-bit, and rapid lateral transfer between 1-bit PEs. The PEs implement the data logical and computational processing with a reduced instruction set. Rapid data transfer between the PE and the associated memory is provided by implementing such elements on a common semi-conductor substrate having shared data address and control signals, thus reducing the complexity of circuitry external to the chip. Flexible and rapid data transfer between and among PEs is provided with a switch element comprising a cross-bar which allows the parallel processor to provide rapid processing of video and other data. A preferred embodiment discussed herein implements the parallel processor using multi-port video DRAM devices as column-aligned parallel processors.

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Durham, NH, United States of America

Michael A Glover