Advanced Micro Devices Corporation

Michael A Filippo

James K Pickett

Benjamin T Sander

Mitchell K Alsup

Michael T Clark

Roger Dwain Isaac

Rama S Gopal

Brian D McMinn

Gregory William Smaus

David Edward Kroesche

Ashraf Ahmed

Arun Radhakrishnan

Greg Smaus

A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.

Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy

A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.

Processor with dependence mechanism to predict whether a load is dependent on older store

A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.

Controlling writes to non-renamed register space in an out-of-order execution microprocessor

A microprocessor may include one or more functional units configured to execute operations, a scheduler configured to issue operations to the functional units for execution, and at least one replay detection unit. The scheduler may be configured to maintain state information for each operation. Such state information may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler should be replayed. If an instance of that operation is currently being executed by one of the functional units when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems may include such a microprocessor.

System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

A microprocessor may include a dispatch unit configured to dispatch load and store operations and a load store unit configured to store information associated with load and store operations dispatched by the dispatch unit. The load store unit includes a STLF (Store-to-Load Forwarding) buffer that includes a plurality of entries. The load store unit is configured to generate an index dependent on at least a portion of an address of a load operation, to use the index to select one of the plurality of entries, and to forward data included in the one of the plurality of entries as a result of the load operation.

Store-to-load forwarding buffer using indexed lookup

A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.

Speculation pointers to identify data-speculative operations in microprocessor

A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.

Cache memory subsystem including a fixed latency R/W pipeline

A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.

Load store unit with replay mechanism

A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.

System and method for handling exceptional instructions in a trace cache based processor

An integrated circuit may have separate clock control for a number of different functional units. Ancillary to some of the functional units may be an activity detector and clock control unit which monitors input to its functional unit to determine when the functional unit will be inactive. When an activity detector and clock control unit determines that a particular functional unit is or will be inactive, it may disable clocking to its functional unit while the functional unit is inactive. When activity detector and clock control unit determines that activity will resume for its functional unit, it enables clocking to its functional unit. Thus, the activity detector and clock control unit for each such functional unit functions to control clocking to its respective functional unit so that during periods of inactivity, inactive functional units are not clocked to reduce the overall static and/or dynamic power consumption for the integrated device.

Clock control of functional units in an integrated circuit based on monitoring unit signals to predict inactivity

An integrated circuit may have separate power control for a number of different functional units. Ancillary to some of the functional units may be an activity detector and power control unit which monitors input to its functional unit to determine when the functional unit will be inactive. When an activity detector and power control unit determines that a particular functional unit is or will be inactive, it may disable power to its functional unit while the functional unit is inactive. When activity detector and power control unit determines that activity will resume for its functional unit, it enables power to its functional unit. Thus, the activity detector and power control unit for each such functional unit functions to control power to its respective functional unit so that during periods of inactivity, inactive functional units are powered down to reduce the overall static and/or dynamic power consumption for the integrated device.

Apparatus and method for decreasing power consumption in an integrated circuit

A microprocessor may include several execution units and a scheduler coupled to issue operations to at least one of the execution units. The scheduler may include several entries. A first entry may be allocated to a first operation. The first entry includes a source status indication for each of the first operation's operands. Each source status indication indicates whether a value of a respective one of the first operation's operands is speculative. The scheduler is configured to update one of the first entry's source status indications to indicate that a value of a respective one of the first operation's operands is non-speculative in response to receiving an indication that a value of a result of a second operation is non-speculative.

Scheduler for use in a microprocessor that supports data-speculative execution

A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may be scheduled to execute an instruction as a single double-wide execution unit or as two independently schedulable single-wide execution units. Functional unit portions may be independently schedulable for execution of instructions operating on a first data type (e.g. SISD instructions). For single-wide instructions, functional unit portions may be scheduled independently. An issue lock mechanism may lock functional unit portions together so that they form a single multi-wide functional unit. For certain multi-wide instructions (e.g. certain SIMD instructions), an instruction operating on a multi-wide or vector data type may be scheduled so that the full multi-wide operation is performed concurrently by functional unit portions locked together as a one wide functional unit.

Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor

In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.

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Manchaca, TX, United States of America

Michael A Filippo