Texas Instruments Corporation

Michael A Denio

Brian Jason Karguth

Charles Lance Fuoco

Samuel Paul Visalli

James G Littleton

Maneesh Soni

Douglas C Crawford

Pierre Bertrand

Michael D Asal

Denis R Beaudoin

Jerry R Van Aken

Thomas M Albers

Akila Subramaniam

William S Egr

David J Halliday

Graham Short

An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Circuit device with multiple parallel data paths

Integrated circuit device with multiple direct memory access (DMA) data paths

Split direct memory access (DMA) with streaming interconnect

Split direct memory access (DMA)

Systems and methods for header compression are described. In various implementations, these systems and methods may be applicable to wireless backhaul systems. For example, a method may include receiving a packet at a backhaul modem from an Ethernet switch, the packet having an uncompressed header comprising a concatenation of at least an Ethernet and an Internet Protocol (IP) header, and a payload; parsing the uncompressed header into a plurality of fields, the plurality of fields including a static field and a derivable field; removing the static field and the derivable field from the uncompressed header; adding a compressed field to the uncompressed header to create a compressed header; and transmitting the packet with the compressed header and the payload over a wireless link.

Header compression for wireless backhaul systems

A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.

Method for infrastructure messaging

A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. Packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory.

Managing free packet descriptors in packet-based communications

A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.

Hardware queue management with distributed linking information

The present invention includes a method and system for routing broadcast packets in a network ( ) using a switching device ( ) which is operable to interconnect sub-portions ( ) of the network ( ). Each network ( ) sub-portion ( ) is connected to at least one of a plurality of switch ports ( ) on the switching device ( ). The switching device ( ) is further operable to forward certain ones of the broadcast packets between the sub-portions ( ) of the network ( ) via the switch ports ( ) in accordance with a forwarding algorithm and to forward all other of the broadcast packets to a processor ( ). The processor ( ) is communicatively connected to the switching device ( ) and is operable to forward the other ones of the broadcast packets in accordance with a set of pre-defined broadcast routing heuristics.

Broadcast traffic reduction in a communications network

Apparatus and a method are disclosed for establishing communication between a sending system and a receiving system. Upon initiation of the communication, the sending system sequentially monitors the receiving system for a response from one of a human interface, a non-cooperating system or a cooperating system. If a response from a human interface within the receiving system is received by the sending system, the sending system transmits a message to a human. If a response is not received from a human interface but is received from a non-cooperating system within the receiving system, the sending system transmits a message to an answering machine. If a response is not received from a human interface or a non-cooperating system, but is received from a cooperating system within the receiving system, information is exchanged between the sending system and the cooperating system in an attempt to establish communication.

Telephone voice mail delivery system

A software product and method for operating a computer, so that a first program operating in a first operating mode having a first addressing format may call code located in a second program operating in a second operating mode having a second addressing format. An argument converter converts all arguments in a stack used in inter-process communication from the first addressing format to the second addressing format. A call gate converts the desired return address into the second addressing format. Thus the called second program properly recognizes the received data and upon completion generates the correct return address.

Apparatus and method enabling a computer to transfer control between two

A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. A set of generic entry point commands is provided. Each extended function is associated with an entry point command, that is appropriate for the function's argument format and return requirements, if any. Each entry point command invokes a communications routine that handles the transfer of argument data and return values, if any, between processors.

System for extending software calls to functions on another processor by

A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.

First processor for dividing long argument data into packets and storing

An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.

Multiprocessor software interface for a graphics processor subsystem

A method of partitioning a software program, so that a main program may be executed on a first processor, and at least one designated function may be executed on a second processor. The subprogram to be executed by the second processor is selected from a main program associated with a first processor and identified globally to both processors. The subprogram is given a call from the main program that creates a software environment that is compatible to both processors. More specifically, the method entails creating an argument passing means, via the function call, so that relevant information about the subprogram parameters may be communicated to the second processor.

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Sugar Land, TX, United States of America

Michael A Denio