Efficient Power Conversion Corporation

Michael A De Rooji

Robert A Beach

Jianjun Cao

Alexander Lidow

Alana Nakata

Seshadri Kolluri

Guangyuan Zhao

Robert Strittmatter

Yanping Ma

Chunhua Zhou

Ming-Kun Chiang

Jiali Cao

Fang Chang Liu

Agus Jauhar

Stephen L Colino

A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

GaN device with reduced output capacitance and process for making same

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

GaN transistors with polysilicon layers for creating additional components

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Palm Springs, CA, United States of America

Michael A De Rooji