Sun Microsystems, Inc.

Michael A Csoppenszky

Kevin B Normoyle

Rajasekhar Cherabuddi

Tzungren A Tzeng

Jui-Cheng Su

Jaybharat Boddu

Alex S Han

Prakash Narain

A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.

DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains

A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.

Method and apparatus for a testable high frequency synchronizer

Low-latency, high-throughput, integrated cache coherent I/O system for a

Bi-directional data transfers between a first system and a second system, which have asynchronous clock domains, are performed using a single dual-port memory. A direction control circuit, which is connected between the first and second systems, determines the desired direction of data transfer and generates one or more direction signals representative of this direction. A write control circuit is coupled to receive a direction control signal, as well as write control signals from the first and second systems. Similarly, a read control signal is coupled to receive a direction control signal, as well as read control signals from the first and second systems. If data transfer is to proceed from the first system to the second system, the write control circuit gives the first system control over the write port of the dual-port memory, and the read control circuit gives the second system control over the read port of the dual-port memory in response to the direction control signals. Conversely, if data transfer is to proceed from the second system to the first system, the write control circuit gives the second system control over the write port of the dual-port memory, and the read control circuit gives the first system control over the read port of the dual-port memory in response to the direction control signals.

Structure and method for bi-directional data transfer between

A simplified or pseudo least-recently-used (LRU) process and circuit in a cache memory or translation lookaside table (TLB) maintains status bits to identify which entries are valid and which entries have been recently used. If none of the entries are invalid, only entries not indicated as recently used are replaced (or overwritten). When all entries are indicated as valid and recently used, status bits other than the status bits for the entry last accessed are changed to indicate that the corresponding entries have not been recently used. Accordingly, those entries can be replaced, but the most recently used entry still cannot be replaced. This makes the pseudo LRU process closer to a full LRU process when compared to pseudo LRU processes which clear all status bits simultaneously. Complexity for the LRU process is not greatly increased because the address generated for the most recent access of an entry can be used to identify the bit which is not changed.

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Los Gatos, CA, United States of America

Michael A Csoppenszky