Digital Equipment Corporation

Michael A Case

Hamid Partovi

William Ralph Wheeler

Steven W Butler

Rajesh Khanna

Michael Leary

A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.

Fast tag compare and bank select in set associative cache

The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. 'Early' address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. 'Late' address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of 'late' address bits is increased relative to the number of 'early' address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses. The 'late' address bits, for example, are a translated portion of a virtual address translated by a translation buffer, and the 'early' address bits are an untranslated portion of the virtual address. Routing problems are avoided by extending the data lines in parallel with the bit lines over regions of the integrated circuit substrate allocated to the memory cells in the array, and forming the data lines in a metalization layer separate from and over a metalization layer of the bit lines. Each data line is multiplexed to multiple bit line segments to eliminate a final multiplexer to input/output lines.

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Grafton, MA, United States of America

Michael A Case