Sun Microsystems, Inc.

Philips Electronics North America Corporation

Analog Bits Inc.

Integrated Device Technology, Inc.

Other

Koninklijke Philips Corporation N.v.

Nytell Software LLC

Vertex Semiconductor Corporation

Michael A Ang

Alexander Dougald Taylor

Jonathan E Starr

Sai V Vishwanthaiah

Eino Jacobs

Alan C Rogers

David J Pilling

Yen C Lee

Hari Hampapuram

Raymond A Heald

Roger Y Lo

Scott Revak

Kevin W Glass

A clock device including: an LC network comprising: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.

Multi-resonant oscillator/clock

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

Method and apparatus for low latency charge coupled decision feedback equalization

A clock device includes an LC network that has a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, the second, and the third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, wherein the LC network is configured to simultaneously resonate at a first frequency and a second frequency that is substantially three times the first frequency, and wherein the clock signal is provided between the first and the third inductive portions by combining a first signal component and a second signal component that is a third harmonic of the first signal component and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.

A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.

Multi-variable multi-wire interconnect

A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Compressed instruction format for use in a VLIW processor

A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit. The driver also includes a pull down circuit coupled to receive at least one of the plurality of control codes. The pull down circuit includes at least one pull down output circuit and a parallel pull down circuit, the parallel pull down circuit being controllable to adjust the impedance of the pull down circuit. The output impedance of the driver is further controlled during transitional phases of turning on and turning off the pull down circuit and the pull up circuit under a plurality of process, voltage and temperature (PVT) conditions.

Dynamic termination logic driver with improved impedance control

An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines. The structures and methods are useful on a power supply board to attenuate periodic ripple voltages produced by a DC-DC converter. In general, the structures and methods are applicable in any application with a period ripple voltage.

Voltage regulator circuit for attenuating inductance-induced on chip supply variations

A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently vary small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Method for differentiating a differential voltage signal using current based differentiation

Differencing non-overlapped dual-output amplifier circuit

A method may be provided which controls the output impedance of a driver which includes within the driver an impedance circuit and a slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a method also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Method for an output driver with improved impedance control

A driver may be provided which controls output impedance of a driver which includes within the driver an impedance circuit and slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Output driver with improved impedance control

A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages are supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.

Growing community of inventors

Santa Clara, CA, United States of America

Michael A Ang