Dupont Photomasks, Inc.

Toppan Photomasks, Inc.

Micha Oren

Dan Rittman

Danny Rittman

A photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufactured with the photomask are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule. A feature located in the identified region is moved based on a second design rule from a first position to a second position in the mask layout file to create a space in the identified region. A grounding feature is placed in the space and automatically connected to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.

Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same

A system and method for correcting connectivity errors in a mask layout are disclosed. The method includes comparing a first connection in a mask layout file to a second connection in a schematic netlist. A connectivity error is identified if the first connection does not match the second connection and the identified connectivity error is automatically corrected in the mask layout file.

System and method for correcting connectivity errors in a mask layout file

A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are placed in the space in the identified region.

Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same

A system and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit are disclosed. The method includes analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are automatically placed in the space in the identified region.

System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit

A photomask and integrated circuit manufactured by eliminating design rule violations during construction of a mask layout block are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a selected position for a polygon in a mask layout block, identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file, and automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation is identified.

Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block

A system and method for eliminating design rule violations during construction of a mask layout block are disclosed. The method includes analyzing a selected position for a polygon in a mask layout block and obtaining one or more design rules associated with the polygon from a technology file. The method provides a hint area associated with the selected position for the polygon that graphically represents a space in the mask layout block where the selected position complies with the design rule violation.

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Cupertino, CA, United States of America

Micha Oren