Apple Inc.

Anobit Technologies Ltd.

Lantiq Israel Ltd.

Runai Labs Ltd.

Micha Anholt

Naftali Sommer

Eyal Gurgi

Ofir Shalvi

Uri Perlmutter

Oren Golov

Shai Winter

Tal Inbar

Ronen Dar

Moti Teitel

Gil Semo

Dotan Sokolov

Yoav Kasorla

Barak Baum

Tomer Ish-Shalom

Barak Rotbard

Or Ordentlich

Avraham Poza Meir

Shai Ojalvo

Koby Vainapel

Gilad Kirshenberg

Maya Barkon

Yoel Boger

Ariel Maislos

Alexander Paley

Yael Shur

Yonathan Tate

Moshe Neerman

Yoav Feinmesser

Eran Gerson

Asaf Landau

Meir Dalal

Alex Radinski

Doron Fischer

Camuel Gilyadov

A method for training a Neural-Network (NN), the method includes receiving a plurality of NN training tasks, each training task including (i) a respective preprocessing phase that preprocesses data to be provided as input data to the NN, and (ii) a respective computation phase that trains the NN using the preprocessed data. The plurality of NN training tasks is executed, including: (a) a commonality is identified between the input data required by computation phases of two or more of the training tasks, and (b) in response to identifying the commonality, one or more preprocessing phases are executed that produce the input data jointly for the two or more training tasks.

Sharing preprocessing, computations, and hardware resources between multiple neural networks

Embodiments for accurately performing time of flight estimations are provided. These embodiments include using a first wireless device to monitor a wireless link and subsequently generate a wireless link estimation based on the monitoring. The embodiments also include deriving a correction metric based on the generated wireless link estimation and transmitting the correction metric from the first wireless device to a second wireless device. The second wireless device may then calculate a time of arrival of a first signal received from the first wireless communication device and correct any errors associated with the time of arrival calculation using the received correction metric. Further, the second wireless device may transmit the corrected time of arrival back to the first wireless device, such that the first wireless device can use the corrected time of arrival to estimate the time of flight of the first signal.

Time of flight estimation using an asymmetric scheme

A decoder includes circuitry and a soft decoder. The circuitry is configured to receive channel hard decisions for respective bits of a Generalized Low-Density Parity Check (GLDPC) code word that includes multiple component code words, including first and second component code words having one or more shared bits, to schedule decoding of the GLDPC code word, and following the decoding, to output the decoded GLDPC code word. The soft decoder is configured to receive the channel hard decisions corresponding to the first component code word, to further receive soft reliability measures that were assigned to the shared bits in decoding the second component code word, and to decode the first component code word based on the channel hard decisions and the soft reliability measures.

GLDPC soft decoding with hard decision inputs

A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

On-the-fly evaluation of the number of errors corrected in iterative ECC decoding

A method includes receiving a first element of a Galois Field of order q, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qand an integer p, where p is a prime number which divides q&#x2212;1. The second element z is raised to a ppower to form a third element. If the third element equals the first element, the second element multiplied by a proot of unity raised to a respective power selected from a set of integers between 0 and p&#x2212;1 is output as at least one root of the first element.

Cubic root of a galois field element

A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Management of data storage in memory cells using a non-integer number of bits per cell

Embodiments described herein relate to a system and method for improving a rate of success in receiving response packets, such as 802.11 Acknowledge (ACK), Block Acknowledge (BACK), and Clear-To-Send (CTS) packets. In one embodiment, a wireless device may transmit one or more first packets according to a wireless communication protocol, and may then receive a second packet. The wireless device may determine that the receiving follows the transmitting by a specific duration of time that is specified by the wireless communication protocol for a response packet to follow one or more communication packets to which it responds. Based at least in part on this determining, the wireless device may further determine that the second packet is a response packet responding to the one or more first packets, without decoding a portion of the second packet that identifies a packet type of the second packet.

Robust decoding of wireless LAN response packets

Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

High-performance ECC decoder

A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines. Data is stored in one or more memory cells of the array using one or more programming levels. In response to a determination that a first memory cell of the one or more memory cells is subject to distortion, a second memory cell may be programmed to a predetermined programming level.

Programming memory cells dependent upon distortion estimation

A method, including factoring an order of a multiplicative group of a Galois Field to produce a first integer factor p and a second integer factor q, wherein the multiplicative group includes (2&#x2212;1) elements, m a non-negative integer, so that 2&#x2212;1=pq. The method further includes receiving an element x of the Galois Field expressible as &#x3b1;, where &#x3b1; is a primitive element of the group, i is a first non-negative integer less than p, and j is a second integer less than q. An inverse or a logarithm of the element x is calculated as a function of qi and j.

Implementation of log and inverse operation in a Galois Field

A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.

Protection against word line failure in memory devices

A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

Power-optimized decoding of linear codes

A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

Configurable and low power encoder for cyclic error correction codes

A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.

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Tel Aviv, Israel

Micha Anholt