International Business Machines Corporation

Globalfoundries Inc.

Miaomiao Wang

Huimei Zhou

Alexander Reznicek

Tenko Yamashita

Hui Zang

Jingyun Zhang

Chih-Chao Yang

Zuoguang Liu

Ruilong Xie

Chun-chen Yeh

Julien Frougier

Chia-Yu Chen

Takashi Ando

Choonghyun Lee

Reinaldo Ariel Vega

Donald Francis Canaperi

Pouya Hashemi

Veeraraghavan S Basker

Junli Wang

Praneet Adusumilli

Oscar Van Der Straten

Su Chen Fan

Huiming Bu

Xuefeng Liu

Jin Haeng Cho

Kangguo Cheng

Brent A Anderson

Effendi Leobandung

Carl John Radens

Chen Zhang

Nicolas J Loubet

Dechao Guo

Hemanth Jagannathan

Terence B Hook

Ruqiang Bao

Heng Wu

Andrew Mark Greene

Christopher Joseph Waskiewicz

Lan Yu

Yoo-Mi Lee

Liqiao Qin

A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.

Stacked complementary field effect transistors

A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

Static random access memory device with stacked FETs

An in-situ chip design is provided for self-heating free characterization of a device under test (DUT) with a short time constant. The in-situ chip design includes a pulse generator configured to output a pulse to the DUT and a buffering circuit arranged between the pulse generator and the DUT. The buffering circuit includes a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.

In-situ chip design for pulse IV self-heating evaluation

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.

Semiconductor structure having stacked power rails

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Electrostatic discharge diode having dielectric isolation layer

Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Self-aligned gate contact for VTFETs

Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Resistance tunable fuse structure formed by embedded thin metal layers

A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Nanosheet transistor with ferroelectric region

Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Planar devices with consistent base dielectric

A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.

A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.

Decoupling BTI and HCI mechanism in ring oscillator

Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Layout design for threshold voltage tuning

A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts in the fuse stack structure.

A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse electrical contacts in the fuse stack structure.

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Albany, NY, United States of America

Miaomiao Wang