Freescale Semiconductor,inc.

Nxp Usa, Inc.

Miaolin Tan

Peidong Wang

Zhe Ge

Zhihong Cheng

Huabin Du

Xiaoxiang Geng

Yali Wang

Zhiwei Lu

Juan Fu

A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.

Level shifter spare cell

An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or 'from' power domain, while other circuits and devices are connected to a voltage supply of the second or 'to' power domain.

Low leakage isolation cell

A multi-bit clock gating cell is used in an integrated circuit (IC) in place of single bit clock gating cells to reduce power consumption. A physical design method is used to form a clock tree of the IC. Initial positions of clock gating cells are defined with respective initial clock input paths. Selected clock gating cells are moved to modified positions in which they may be adjoining. Adjoining cells are merged by substituting a multi-bit clock gating cell having multiple gating signal inputs, corresponding gated clock outputs, and a common clock input path. A net reduction is obtained for the overall capacitance of the clock path due to reduction of the upstream capacitance of the clock path and of the resulting multi-bit clock gating cell itself, compared with the aggregate capacitance of the clock paths of the corresponding clock gating cells before moving and merging.

Integrated circuit with multi-bit clock gating cells

A multi-module integrated circuit (IC) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. The module also has driving circuitry with one or more package-aware cells. The IC has a package-aware controller that generates control signals for the package-aware cells that ensure that the outputs from the package-aware cells are forced to particular values (i.e., either logical-0 or logical-1) that cause the low power input vector to be applied to the driven circuitry when the IC is assembled in a package in which the module is disabled. In this way, module leakage power is reduced for package types in which certain modules are disabled.

Package-aware state-based leakage power reduction

A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

State retention power gated cell

An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

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Suzhou, China

Miaolin Tan