International Business Machines Corporation

Maxim Integrated Products, Inc.

Miaochen Wu

Aria Eshraghi

Theodore L Tewksbury

Brian L Dellacroce

A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters

A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

Sigma delta modulator with SAW filter

A bandpass delta-sigma modulator converts a signal of a nominal frequency to an oversampled digital signal. Digital decimation filter decimates the signal by multiplying the signal by first and second modulating signals. The modulating signals are selected to have a frequency which can produce a baseband signal with a nominal frequency of &pgr;*/3. By using an oversampling rate of 6 times the carrier frequency signal rate, the modulation signal of a frequency &pgr;*/3 produces a real and imaginary signal. The real and imaginary signal can be filtered in first and second filtering decimation circuits reducing the number of signal processing paths for the signal. The decimated signal is further filtered and decimated using conventional digital filtering techniques.

Decimation filter for a bandpass delta-sigma ADC

By sampling at six times the carrier frequency cosine and sine multiplication circuits are found to be constructable from simple shift and inversion circuit. Shifting and inversion are controlled by means of a simple finite state machine or other circuits cycling through a six cycle periodic sequence.

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Acton, MA, United States of America

Miaochen Wu