Oracle International Corporation

Sun Microsystems, Inc.

Miao Rao

Gajendra Prasad Singh

Shree Kant

James Ballard

Aparna Ramachandran

Kiran Kishore Vedantam

Guneet Singh

Wanyun Singh

Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.

Methods and systems for flexible and repeatable pre-route generation

A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.

Low power memory design with asymmetric bit line driver

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San Jose, CA, United States of America

Miao Rao