Hewlett Packard Enterprise Development LP

Tetramem Inc.

Miao Hu

John Paul Strachan

Ning Ge

Jianhua Yang

Richard Stanley Williams

Zhiyong Li

Wenbo Yin

Raymond G Beausoleil

Naveen Muralimanohar

Brent Buchanan

Chin-Hui Chen

Tsung-Ching Huang

Glen Eric Montgomery

Hengfang Zhu

Stanley Williams

The present disclosure relates to voltage-mode crossbar circuits that may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of sensing circuits configured to amplify bit line voltages settled on the bit lines in response to an application of input voltages to the cross-point devices via the word lines and generate digital outputs representative of the amplified bit line voltages. Each cross-point device is connected to one of the word lines and one of the bit lines and may include a resistive random-access memory (RRAM) device. Each cross-point device may further be connected to a local select line that may enable a group of cross-point devices connected to one or more bit lines. A cross-point device may be enabled when both a global select line and the local select line connected to the cross-point device are enabled.

Voltage-mode crossbar circuits

In accordance with some embodiments of the present disclosure, an apparatus for performing convolution operations is provided. The apparatus includes a first crossbar circuit comprising a first plurality of cross-point devices; a second crossbar circuit comprising a second plurality of cross-point devices; and a word line logic to apply input signals to the first crossbar circuit and the second crossbar circuit. The word line logic is configured to provide input signals representative of input data to be convolved using one or more two-dimensional convolution kernels and one or more depth-wise convolution kernels. The first crossbar circuit is configured to output a first plurality of output signals representative of a convolution of the input data and the two-dimensional convolution kernels. The second crossbar circuit is configured to output a second plurality of output signals representative of a convolution of the input data and the depth-wise convolution kernels.

Crossbar circuits for performing convolution operations

Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters.

Auto-calibrating crossbar-based apparatuses

In one example, a device to process analog sensor data is described. For example, a device may include at least one analog sensor to generate a first set of analog voltage signals and a crossbar array including a plurality of memristors. In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.

Memristor crossbar arrays to activate processors

Methods of using large output resistance with adjusted conductance mapping value to reduce the current in crossbar array circuit are disclosed. An example method of simulating a crossbar array circuit having a crossbar array, includes steps of: S1. testing the crossbar array; S2. calibrating a simulation model; S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3; S4. determining a fixed ratio of ideal current from the simulation result; S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix; S6. programming the conductance matrix to the crossbar array; S7. passing an input signal to the crossbar array and generating a computing result; and S8. checking the quality of computing results.

Reducing current in crossbar array circuits with large output resistance

An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.

Analog multiplier-accumulators

A device according to examples of the present disclosure includes a crossbar array including a cell. The cell includes a first resistance switch and a second resistance switch connected in series with the first resistance switch. The first and second resistance switches have different switching characteristics. One of the first and second resistance switches may act as a switch, while the other of the first and second resistance switches may weight the switching behavior of the one that acts as the switch.

Device with multiple resistance switches with different switching characteristics

A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N&#xd7;M memory elements to store information corresponding to values contained in an N&#xd7;M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N&#xd7;1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

Double bias memristive dot product engine for vector processing

A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.

Memristor crossbar array for performing a fourier transformation

A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.

Memcapacitive cross-bar array for determining a dot product

A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.

Memristive dot product engine for vector processing

Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

Linear transformation accelerators

According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

Crossbar array operations using ALU modified signals

A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.

Crossbar arrays for calculating matrix multiplication

Example implementations of the present disclosure relate to improved computational accuracy in a crossbar array. An example system may include a crossbar array, having a plurality of memory elements at junctions, usable in performance of computations. The example system may further include a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array and a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array. An adjust engine of the example system may be used to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element.

Growing community of inventors

Palo Alto, CA, United States of America

Miao Hu