Altera Corporation

Mian Z Smith

Wanli Chang

Gregory W Starr

Tim Tri Hoang

Kazi Asaduzzaman

Richard Y Chang

Kang Wei Lai

Kang-Wei Lai

Sergey Yuryevich Shumarayev

Myron Wai Wong

Ninh D Ngo

Leon Zheng

Stephanie T Tran

Guu Lin

Joseph M Ingino

Richard Chang

To improve noise rejection, a native (or undoped) NMOS transistor is used as a source follower in place of a conventional common source PMOS transistor in a voltage regulator circuit. The native transistor has a threshold voltage of approximately 0 volts which allows the maximum voltage output of the regulator to be higher by one threshold voltage of a conventional NMOS transistor than might be obtained from a voltage regulator that used a conventional NMOS transistor. Alternatively, a depletion transistor can be used to provide even higher output. In another illustrative embodiment, a conventional bandgap reference circuit is modified by replacing a common source transistor connected to the output of an op amp with a native MOS transistor connected as a source follower.

Voltage regulator with high noise rejection

Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

Techniques for compensating delays in clock signals on integrated circuits

A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

Loop circuits that reduce bandwidth variations

A differential input buffer that can operate at lower power supply voltages and can receive differential input signals with wide common mode rage. In various embodiments, the invention combines native or depletion mode metal-oxide-semiconductor (MOS) transistors with the conventional enhancement mode n-channel (NMOS) and p-channel (PMOS) transistors in the design of the input buffer. The native or depletion MOS transistors can operate at lower power supply voltages and increase the input common-mode voltage range.

Differential input buffers for low power supply

A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

Highly configurable PLL architecture for programmable logic

Various embodiments for differential output circuits with reduced transistor sizes and reduced DC currents provide efficient and flexible differential driver circuits. AC current boosting enables the switching transistors that drive the output nodes to be smaller in size. The AC current boost circuitry is shared by both switching current paths in the differential output circuit to reduce size and parasitic effects. Similarly, DC current circuitry is also shared by both switching current paths. The AC boost circuit and the DC bias circuit are made programmable to enable the output circuit to support multiple I/O standards with different specifications.

Differential output buffer with super size

Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.

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Los Altos, CA, United States of America

Mian Z Smith