Hynix Semiconductor Inc.

Skhynix Inc.

Yonsei University

Nhn Corporation

Mi Sun Yoon

Sang Oh Lim

Chul Woo Yang

Byoung Kwan Jeong

Dong Hyuk Chae

Wook Jin Shin

Chung Yong Lee

Seung Bae Lee

Jae Wan Jang

Chang Guen Song

Kyu Won Moon

Sung Kwan Kim

Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.

Memory device and method of operating the same

Provided are a method and an apparatus for transmitting a signal suitable for an indoor environment. The method for transmitting a signal according to an exemplary embodiment of the present invention includes: preprocessing a signal using a signal power to sidelobe power ratio (SSR) parameter defining a signal to sidelobe ratio to minimize an inter-symbol interference and prevent performance deterioration due to reduction in signal strength; and transmitting the preprocessed signal to a receiving apparatus through a predetermined channel.

Method and apparatus for transmitting and receiving signal

The present invention relates to a user interface server framework and a method of using the framework, which supports a user interface developer to develop a final user interface based on components. The component-based web application development framework used for creating a web page comprises a runtime engine for executing a method of a business object and returning a result of executing the method in response to a user's request; a script component for performing a preprocessing on a user input value before executing the method of the business object, performing a post-processing on the result of executing the method after executing the method of the business object, and dynamically arranging a user interface object; and a core component for initializing the framework and confirming whether the user's request can be processed in the framework.

Component-based web application development framework used for creating web page

A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch.

Method of operating semiconductor memory device

A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

Semiconductor memory device and method of operating the same

A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

Counting circuit and address counter using the same

A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.

Method of programming nonvolatile memory device

A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

A nonvolatile memory device includes a first plane and a second plane, an address decoder configured to decode an externally input address and to output a first plane select signal and a second plane select signal for enabling any one of the first and second planes, a controller configured to output a first plane hold signal and a second plane hold signal for disabling any one of the first and second planes depending on program states of the first plane and the second plane, a first plane control unit configured to enable the first plane in response to a first plane select signal and the first plane hold signal, and a second plane control unit configured to enable the second plane in response to a second plane select signal and the second plane hold signal.

Nonvolatile memory device and method of operating the same

The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.

Growing community of inventors

Gunsan-si, South Korea

Mi Sun Yoon