Samsung Electronics Co., Ltd.

Mi-jung Noh

Kyoung-moon Ahn

Sang-wook Park

Yong-ki Lee

Yun-hyeok Choi

Hong-mook Choi

Bohdan Karpinskyy

Sun-Soo Shin

Young-sik Kim

Xingguang Feng

Dae-hyeon Kim

Hyun-Min Kim

Yun-Ho Youm

Seo-Kyu Kim

Karpinskyy Bohdan

Yong-Soo Kim

Tae-Su Kim

Kitak Kim

Hong-Mook Choi

Hyun-woong Lee

Jung-Sook Lee

An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.

Integrated circuit for physically unclonable function and device including the same

A physical unclonable function (PUF) circuit and a PUF system including the same are provided. The PUF circuit includes a plurality of PUF cells each configured to generate an output voltage by dividing a power voltage, a reference voltage generator configured to generate a first reference voltage by dividing the power voltage, and a comparing unit configured to sequentially compare the output voltages of the plurality of PUF cells with the first reference voltage to output data values of the plurality of PUF cells.

Physically unclonable function circuit, and system and integrated circuit including the same

An apparatus for testing a random number generator includes a correlation test circuit and a randomness determination circuit. The correlation test circuit extracts a first plurality of bit pairs each including two bits spaced apart from each other by a first distance in a bit stream generated by the random number generator, obtains a first sum of differences between respective two bits of the first plurality of bit pairs, and obtains a second sum of differences between respective two bits of a second plurality of bit pairs, the second plurality of bit pairs each including two bits spaced apart from each other by a second distance, different from the first distance, in the bit stream. The randomness determination circuit determines a randomness of the bit stream, based on the first sum and the second sum.

Randomness test apparatus and method for random number generator

Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation. The modular multiplier apparatus for obtaining a quotient and a result of an arithmetic operation of modular multiplication by using a modulus and two arbitrary constants includes: a reduction unit for obtaining a short path carry (SPC) included when a result of a modular arithmetic operation is obtained at a current stage, by using a medium calculation result; a carry predictor for predicting a long path carry (LPC) included when the result of the modular arithmetic operation is obtained at the current stage, by using the medium calculation result; and an accumulator for accumulating the result of the modular arithmetic operation by using the SPC and the LPC, wherein the medium calculation result is obtained by adding a result of a modular arithmetic operation obtained at a previous stage and a partial product of the two constants obtained at the current stage.

Modular multiplier apparatus with reduced critical path of arithmetic operation and method of reducing the critical path of arithmetic operation in arithmetic operation apparatus

Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.

Methods of calculating negative inverse of modulus

A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.

Password system, method of generating a password, and method of checking a password

In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Apparatus and method of authenticating joint test action group (JTAG)

Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(&#x2022;). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.

Data cipher processors

An apparatus, method and a computer program for processing multimedia data is described, where the apparatus may include an input switch which may receive a plurality of transport stream packets corresponding to a plurality of digital multimedia data signals input thereto, and a packet identification (PID) filter unit which may selectively output a given set of TS packets to be demultiplexed from the received plurality of TS packets. A buffer and/or an external memory device may store at least some of the TS packets of the output given set. A conditional access/content protection (CA/CP) unit may read and decrypt the TS packets stored in the buffer, and may encrypt at least some of the decrypted TS packets for storage in the external memory device if the buffer becomes full, to prevent the TS packets to be stored in the external memory device from being copied.

Method, apparatus and computer program for processing multimedia data signals

An engine, register in a memory, and methods for the same are provided. The engine may include a data encryptor, a key encryptor, a data decryptor, a key decryptor, a register, and a control circuit. The data encryptor may encrypt data using a key. The key encryptor may encrypt the key used by the data encryptor. The data decryptor may receive encrypted data from a storage medium and may decrypt the encrypted data. The key decryptor may receive an encrypted key from the storage medium and may decrypt the encrypted key. The register may indicate the status of the key and/or the encrypted key. The control circuit may control the data encryptor, the data decryptor, the key encryptor, the key decryptor, and the register.

Engine, register and methods for the same

An Mblock cipher system and method for encoding content and authenticating a device may use an Mcore. The Mblock cipher system may include a rotate constant selector selecting one or more rotate constants from a plurality of input rotate constants for output based on a selection signal input thereto, a rotate constant ordering device ordering the selected rotate constants and a common rotate constant input thereto based on a received ordering signal and an Mcore generating one or more of an output signal, a validity signal and a round number based on the ordered rotate constants and a plurality of input signals. The system may include a rotate constant scheduler outputting the ordering signal to the rotate constant ordering device in response to the selection signal and the round number.

M6 block cipher system and method for encoding content and authenticating a device

A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items, and may output the stored input key data items as the storage key data items. The key calculating unit may output the calculation key data items as the calculation result. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.

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Yongin-si, South Korea

Mi-jung Noh